Sharp LH79524 - Chapter 7 - External Memory Controller

Version 1.0 7-1
Chapter 7
External Memory Controller
The External Memory Controller (EMC) provides all the interface and control functions for
the both static and dynamic memory devices. The EMC features:
• Dynamic memory interface support including SDRAM and JEDEC low-power SDRAM
• Asynchronous static memory device support including RAM, ROM, and Flash, with or
without asynchronous page mode
• Low transaction latency
• Read and Write buffers to reduce latency and to improve performance
• 8-bit and 16-bit wide static memory support (32-bit support in the LH79524)
• 16-bit wide synchronous SDRAM memory support (32-bit support in the LH79524)
• Static memory features include:
– Asynchronous page mode read
– Programmable wait states
– Bus turnaround delay
– Output enable, and write enable delays
– Extended wait
– Wait states may be extended indefinitely using the nWAIT pin
• Two Chip Selects for synchronous and up to four Chip Selects for static memory devices
• Up to four memory Byte Lane Selects for static memory devices
• Boot in 8-, 16-, or 32-bit mode.
7.1 Theory of Operation
The combined dynamic and static memory controller controls all static and dynamic mem-
ory accesses. Figure 7-1 is a block diagram of the EMC. The EMC contains the following:
• Command sequencer — Rearranges the memory accesses for maximum efficiency.
• Memory Transfer State Machine — Controls the current transfer.
• Static Memory Controller Register Banks — The four static memory controller register
banks hold the static memory registers. These registers allow software to control and
configure the static memory controller.
• Dynamic Memory Controller Register Banks — The two dynamic memory controller reg-
ister banks hold the dynamic memory registers. These registers allow software to control
and configure the dynamic memory controller.