Sharp LH79524 - Table 14-21. DCR Register; Table 14-22. DCR Fields; DMA Control Register (DCR)

Synchronous Serial Port LH79524/LH79525 User’s Guide
14-20 Version 1.0
14.2.2.10 DMA Control Register (DCR)
DCR is the DMA Control Register.
The RXDMAE and TXDMAE bits are not automatically cleared for standard Stream 0
through 3 DMA operations, respectively. These bits should be explicitly cleared by soft-
ware as soon as possible following DMA completion.
On initiating a DMA operation the DMAC:CTRL:ENABLE bit should be set before the RXD-
MAE bit, is set.
Table 14-21. DCR Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
TXDMAE
RXDMAE
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
ADDR 0xFFFC6000 + 0x024
Table 14-22. DCR Fields
BITS NAME DESCRIPTION
31:2
/// Reserved Reading returns 0. Write the reset value.
1TXDMAE
Transmit DMA Enable
1 = DMA for the transmit FIFO is enabled
0 = Transmit DMA disabled
0RXDMAE
Receive DMA Enable
1 = DMA for the receive FIFO is enabled
0 = Receive DMA disabled