Sharp LH79524 - Interrupt Mask Set or Clear Register (IMSC); Table 10-7. IMSC Register; Table 10-8. IMSC Register Definitions

LH79524/LH79525 User’s Guide I
2
S Converter
Version 1.0 10-17
10.2.2.3 Interrupt Mask Set or Clear Register (IMSC)
On a Read, this register gives the current value of the mask on the relevant interrupt. Writ-
ing 1 to the particular bit sets the mask, enabling the interrupt to be read. Writing 0 clears
the corresponding mask. All bits are cleared to 0 when reset.
Table 10-7. IMSC Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
SSPPEM
ECPEM
TXUEM
TXIM
RXIM
RTIM
RORIM
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW
ADDR 0xFFFC8000 + 0x008
Table 10-8. IMSC Register Definitions
BITS NAME DESCRIPTION
31:7 /// Reserved Reading returns 0. Write the reset value.
6 SSPPEM
SSP Protocol Error mask
1 = Master Mode Protocol Error condition interrupt enabled
0 = Master Mode Protocol Error condition interrupt is masked
5ECPEM
External Codec Protocol Error mask
1 = Slave Mode Protocol Error condition interrupt enabled
0 = Slave Mode Protocol Error condition interrupt is masked
4TXUEM
Transmit Underrun Error mask
1 = Tx Underrun condition interrupt enabled
0 = Tx Underrun condition interrupt is masked
3TXIM
Transmit FIFO Interrupt mask (From SSP IMSC:TXIM bit)
1 = Tx FIFO half empty or less condition interrupt enabled
0 = Tx FIFO half empty or less condition interrupt is masked
2RXIM
Receive FIFO Interrupt mask (From SSP IMSC:RXIM bit)
1 = Rx FIFO half full or more condition interrupt enabled
0 = Rx FIFO half full or more condition interrupt is masked
1RTIM
Receive Timeout Interrupt mask (From SSP IMSC:RTIM bit)
1 = Rx FIFO not empty and no read prior to timeout period interrupt is enabled
0 = Rx FIFO not empty and no read prior to timeout period interrupt is masked
0 RORIM
Receive Overrun Interrupt mask (From SSP IMSC:RORIM bit)
1 = Rx FIFO written to while full condition interrupt is enabled
0 = Rx FIFO written to while full condition interrupt is masked