Sharp LH79524 - Interrupt Mask Set;Clear Register (UARTIMSC); Table 16-26. UARTIMSC Register; Table 16-27. UARTIMSC Fields

UARTs LH79524/LH79525 User’s Guide
16-20 Version 1.0
16.3.2.10 Interrupt Mask Set/Clear Register (UARTIMSC)
UARTIMSC is the Interrupt Mask Register. On a read, this register returns the current value
of the mask on the relevant interrupt. Writing 0 to the particular bit masks the interrupt. Writ-
ing 1 enables the corresponding interrupt. All the bits are cleared to 0 following a System
Reset, which masks all interrupts by default.
The combined UARTx UARTINT, presented to the VIC, is the bitwise logical AND of this
register and the Raw Interrupt register, UARTRIS.
Table 16-26. UARTIMSC Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
OEIM
BEIM
PEARIM
FEIM
RTIM
TXIM
RXIM
///
CTS0IM
///
RESET 0000000000000000
RW RO RO RO RO RO RW RW RW RW RW RW RW RO RO RW RO
ADDR
UART 0: 0xFFFC0000 + 0x038
UART 1: 0xFFFC1000 + 0x038
UART 2: 0xFFFC2000 + 0x038
Table 16-27. UARTIMSC Fields
BITS NAME DESCRIPTION
31:11 /// Reserved Reading returns 0. Write the reset value.
10 OEIM
Overrun Error Interrupt Mask When read, returns the current mask for the
OEIM interrupt. Write values:
1 = Enable the OEI interrupt
0 = Mask the OEI interrupt
9 BEIM
Break Error Interrupt Mask When read, returns the current mask for the
BEIM interrupt. Write values:
1 = Enable the BEI interrupt
0 = Mask the BEI interrupt
8 PEARIM
Parity Error/Address Received Interrupt Mask When read, returns the cur-
rent mask for the PEARIM interrupt. Write values:
1 = Enable the PEARI interrupt
0 = Mask the PEARI interrupt
7FEIM
Framing Error Interrupt Mask When read, returns the current mask for the
FEIM interrupt. Write values:
1 = Enable the FEI interrupt
0 = Mask the FEI interrupt