Sharp LH79524 - Figure 7-8. Typical Memory Connection Diagram

External Memory Controller LH79524/LH79525 User’s Guide
7-8 Version 1.0
Figure 7-8. Typical Memory Connection Diagram
nCE
A[15:0]
2M × 32 BURST MASK ROM
64K × 16 SRAM, × 2
128K × 8 SRAM, × 4
IO[15:0]
A[20:0]
nCS0
nOE
nCS1
nWE
nCS2
nBLE3
nBLE2
nBLE1
nBLE0
nOE
nWE
nUB
nLB
nCE
A[20:0] Q[31:0]
D[31:0]
D[31:16]
D[31:24]
D[23:16]
D[15:8]
D[7:0]
D[15:0]
nOE
nCE
A[15:0]
IO[15:0]
nOE
nWE
nUB
nLB
nCE
A[16:0]
IO[7:0]
nOE
nWE
nCE
A[16:0]
IO[7:0]
nOE
nWE
nCE
A[16:0]
IO[7:0]
nOE
nWE
nCE
A[16:0]
IO[7:0]
nOE
nWE
LH79525-93