Sharp LH79524 - Table 11-34. MUXCTL12 Register; Table 11-35. MUXCTL12 Fields; Multiplexing Control 12 Register (MUXCTL12)

I/O Configuration LH79524/LH79525 User’s Guide
11-26 Version 1.0
11.2.2.17 Multiplexing Control 12 Register (MUXCTL12)
The MUXCTL12 Register allows software to configure a number of LH79524/LH79525
pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525.
Table 11-34. MUXCTL12 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD PK0 PD0 ///
RESET
8-Bit
0000000000000000
RESET
16-Bit
0001000000000000
RESET
32-Bit
0101000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0x58
Table 11-35. MUXCTL12 Fields
BIT NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:14 PK0
PK0/D16 Assignment (LH79524 Only)
00 = PK0
01 = D16
10 = Reserved
11 = Reserved
13:12 PD0
PD0/D8 Assignment
00 = PD0
01 = D8
10 = Reserved
11 = Reserved
11:0 /// Reserved Reading returns 0. Write the reset value.