Sharp LH79524 - Multiplexing Control 24 Register (MUXCTL24); Table 11-68. MUXCTL24 Register; Table 11-69. MUXCTL24 Fields

I/O Configuration LH79524/LH79525 User’s Guide
11-52 Version 1.0
11.2.2.34 Multiplexing Control 24 Register (MUXCTL24)
The MUXCTL24 Register allows software to configure a number of LH79524/LH79525 pins.
Table 11-68. MUXCTL24 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// PH1 PH0 PI7 PI6 PI5 PI4 PI3
RESET 0000000000000000
RW RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0xB8
Table 11-69. MUXCTL24 Fields
BIT NAME DESCRIPTION
31:14 /// Reserved Reading returns 0. Write the reset value.
13:12 PH1
PH1/ETHERRXDV Assignment
00 = PH1
01 = ETHERRXDV
10 = Reserved
11 = Reserved
11:10 PH0
PH0/ETHERRX3 Assignment
00 = PH0
01 = ETHERRX3
10 = Reserved
11 = Reserved
9:8 PI7
PI7/ETHERRX2 Assignment
00 = PI7
01 = ETHERRX2
10 = Reserved
11 = Reserved
7:6 PI6
PI6/ETHERRX1 Assignment
00 = PI6
01 = ETHERRX1
10 = Reserved
11 = Reserved
5:4 PI5
PI5/ETHERRX0 Assignment
00 = PI5
01 = ETHERRX0
10 = Reserved
11 = Reserved
3:2 PI4
PI4/ETHERRXER Assignment
00 = PI4
01 = ETHERRXER
10 = Reserved
11 = Reserved
1:0 PI3
PI3/ETHERCRS Assignment
00 = PI3
01 = ETHERCRS
10 = Reserved
11 = Reserved