Sharp LH79524 - Data Mask Signals; Table 7-9. Memory System Examples

LH79524/LH79525 User’s Guide External Memory Controller
Version 1.0 7-27
7.4.4 Data Mask Signals
Depending on the external memory system width and the operand size, one or two mem-
ory cycles may be required for operand transfer. The Data Mask signals (DQM[3:0]) select
the data phase for each cycle, as shown in Table 7-9.
• For 32-bit wide memory systems, only one memory cycle is required for any data trans-
fer width, with the DQM bits configured on write cycles to disable bytes unaffected by
the transfer.
• For 16-bit wide memory systems, DQM[1] is used as the memory system upper data
mask (UDQM) and DQM[0] is used as the lower data mask (LDQM).
• For 32-bit transfers in 16-bit wide memory systems, two memory data phases are
required to complete the memory cycles. Half word (16-bit) and byte-width transfers
complete in one data phase.
Table 7-9. Memory System Examples
MEMORY SYSTEM SIZE DATA BUS
AHB PHYSICAL
ADDRESS
BYTE ENABLES
16M by 16-bit 32MB D[15:0] A[24:1] DQM[1:0]
16M by 32-bit 64MB D[31:0] A[25:2] DQM[3:0]
64M by 16-bit 128MB D[15:0] A[26:1] DQM[1:0]
64M by 32-bit 256MB D[31:0] A[27:2] DQM[3:0]