Version 1.0 5-1
Chapter 5
Direct Memory Access
Controller
The DMA Controller in the LH79524/LH79525 is identical in each SoC; all descriptions in
this chapter apply to both devices. The DMA Controller provides four concurrent data
streams and three modes of transfer:
• Memory to Memory (selectable on Stream 3 only)
• Peripheral to Memory (all streams)
• Memory to Peripheral (all streams)
A built-in data stream arbiter handles all scheduling and conflict resolution. Each stream
can alert the operating system of a transfer error via an interrupt. Table 5-1 lists the
streams and their priority.
There are seven registers for each stream. Software uses these registers to program:
• DMA enable
• Transfer Size (Byte, Half-word, Word)
• Burst Size (1, 4, 8, or 16)
• Address Increment Enable
• Transfer Direction
• Maximum Count
• Terminal Count
DMA transactions use a 16-word First-In, First Out (FIFO) array, with pack and unpack
logic to handle all input/output combinations of byte, half-word, and word transfers. In
addition, there are external DMA Request (DREQ) and Acknowledge (DACK) signals
synchronized with the External Memory Controller’s write and read signals.
Any external peripheral using DREQ and DACK pins must be mapped into the nCS3 mem-
ory space for proper operation. See Section 1-6 for memory space mapping.
Table 5-1. DMA Controller Stream Assignments and Request Priority
DMA REQUESTOR DMA STREAM
SSPRX (highest priority) Stream 0
SSPTX Stream 1
UART0RX/External DREQ Stream 2
UART0TX (lowest priority)/Memory-to-Memory Stream 3
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