Sharp LH79524 - Table 5-2. DMA Memory Map; Table 5-3. DMA Data Stream Register Summary (One Set of Registers for each of the Four Data Streams in Table 5-2)

LH79524/LH79525 User’s Guide Direct Memory Access Controller
Version 1.0 5-5
5.2 Register Reference
This section provides the DMA Controller register memory mapping and bit fields.
5.2.1 Memory Map
Each stream has the identical set of 11 registers. The base address for each stream is
shown in Table 5-2. The 11 registers are summarized in Table 5-3. The address offset
listed is with reference to the particular stream’s base address, shown in Table 5-2. For
example, the address for the DESTLO register for STREAM2 is:
(STREAM2 Base = 0xFFFE1080) + (DESTLO Offset = 0x008) = 0xFFFE1088.
Table 5-2. DMA Memory Map
DATASTREAM BASE ADDRESS DESCRIPTION
STREAM0 0xFFFE1000 Data Stream 0 Register Base Address
STREAM1 0xFFFE1040 Data Stream 1 Register Base Address
STREAM2 0xFFFE1080 Data Stream 2 Register Base Address
STREAM3 0xFFFE10C0 Data Stream 3 Register Base Address
MASK 0xFFFE10F0 DMA Interrupt Mask Register
CLR 0xFFFE10F4 DMA Interrupt Clear
STATUS 0xFFFE10F8 DMA Status Register
Table 5-3. DMA Data Stream Register Summary
(One Set of Registers for Each of the Four Data Streams in Table 5-2)
ADDRESS
OFFSET FROM
STREAM BASE
NAME DESCRIPTION
0x000 SOURCELO Source Base Address Register, lower 16 bits
0x004 SOURCEHI Source Base Address Register, higher 16 bits
0x008 DESTLO Destination Base Address Register, lower 16 bits
0x00C DESTHI Destination Base Address Register, higher 16 bits
0x010 MAX Maximum Count Register
0x014 CTRL Control Register
0x018 CURSHI Current Source Address Register, higher 16 bits
0x01C CURSLO Current Source Address Register, lower 16 bits
0x020 CURDHI Current Destination Address Register, higher 16 bits
0x024 CURDLO Current Destination Address Register, lower 16 bits
0x028 TCNT Terminal Count
0x2C - 0x3C /// Reserved — Do not access