External Memory Controller LH79524/LH79525 User’s Guide
7-34 Version 1.0
7.5.2.5 Dynamic Refresh Register (DYNMREF)
This register configures dynamic memory operation.
This register should only be modified during system initialization, or when there are no
current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that changing
parameters will not corrupt external data. Low-Power Mode automatically refreshes
SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh (DYNMC-
TRL:SR = 1) prior to entering Disable. However, these control bits can, if necessary, be
altered during normal operation.
Writing a value of 0x000 disables refreshing. Programming any other value, ‘n’, results in
a delay between refresh cycles of 16 × n. For example, for the refresh period of 16 µs, and
an HCLK frequency of 50 MHz, the following value must be programmed into this register:
(16 × 10
-6
× 50 × 10
6
) ÷ 16 = 50, or 0x032
Table 7-19. DYNMREF Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// REFRESH
RESET 0000000000000000
TYPE RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFF1000 + 0x024
Table 7-20. DYNMREF Fields
BITS NAME FUNCTION
31:11 /// Reserved Reading returns 0. Write the reset value.
10:0 REFRESH
Refresh Timer (×16)
For REFRESH = 0x000: Refresh disabled
For REFRESH between 0x001 and 0xFFF:
HCLK cycles between SDRAM refresh cycles = 16 × (REFRESH)
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