Sharp LH79524 - Core Clock Configuration Register (CORECONFIG); Table 13-50. CORECONFIG Register; Table 13-51. CORECONFIG Fields

Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide
13-32 Version 1.0
13.2.2.21 Core Clock Configuration Register (CORECONFIG)
This register can be programmed to select either the Standard Mode or the FastBus exten-
sion for the ARM720T bus interface. In Standard mode, either a synchronous or asynchro-
nous operation can be selected. When changing from Standard Mode to FastBus, the CPU
clock must always be greater than or equal to the system bus clock.
Table 13-50. CORECONFIG Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// CCLK
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO WO WO WO WO WO WO WO WO
ADDR 0xFFFE2000 + 0x88
Table 13-51. CORECONFIG Fields
BITS NAME DESCRIPTION
31:2 /// Reserved Reading is indeterminate. Write the reset value.
1:0 CCLK
Core Clock Configuration Program this field to configure the ARM720T
core clock.
00 = Standard Mode, asynchronous operation
01 = FastBus extension mode
10 = Standard Mode, synchronous operation
11 = FastBus extension mode