Sharp LH79524 - Raw Interrupt Status Register (RIS); Table 12-12. RIS Register; Table 12-13. RIS Fields; Table 12-14. MIS Register

Real Time Clock LH79524/LH79525 User’s Guide
12-6 Version 1.0
12.2.2.6 Raw Interrupt Status Register (RIS)
Reading this register gives the current raw status value of the RTC interrupt prior to mask-
ing. Writing has no effect.
12.2.2.7 Masked Interrupt Status Register (MIS)
Reading the MIS register gives the current masked status value of the RTC interrupt. Writ-
ing has no effect.
Table 12-12. RIS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// RIS
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFE0000 + 0x14
Table 12-13. RIS Fields
BITS NAME DESCRIPTION
31:1 /// Reserved Reading returns 0. Values written cannot be read.
0RIS
Raw Interrupt Status Contains the raw state (prior to masking) of the RTC Interrupt.
1 = RTC Interrupt asserted
0 = RTC Interrupt not asserted
Table 12-14. MIS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// MIS
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFE0000 + 0x18
Table 12-15. MIS Fields
BITS NAME DESCRIPTION
31:1 /// Reserved Reading returns 0. Values written cannot be read.
0MIS
Masked Interrupt Status Contains the masked interrupt state of the RTC Interrupt.
1 = RTC Interrupt unmasked and asserted
0 = RTC Interrupt masked or not asserted