Sharp LH79524 - Multiplexing Control 23 Register (MUXCTL23); Table 11-64. MUXCTL23 Register; Table 11-65. MUXCTL23 Fields

I/O Configuration LH79524/LH79525 User’s Guide
11-48 Version 1.0
11.2.2.32 Multiplexing Control 23 Register (MUXCTL23)
The MUXCTL23 Register allows software to configure a number of LH79524/LH79525 pins.
Table 11-64. MUXCTL23 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0xB0
Table 11-65. MUXCTL23 Fields
BIT NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:14 PG1
PG1/ETHERTXCLK Assignment
00 = PG1
01 = ETHERTXCLK
10 = Reserved
11 = Reserved
13:12 PG0
PG0/ETHERTXEN Assignment
00 = PG0
01 = ETHERTXEN
10 = Reserved
11 = Reserved
11:10 PH7
PH7/ETHERTX3 Assignment
00 = PH7
01 = ETHERTX3
10 = Reserved
11 = Reserved
9:8 PH6
PH6/ETHERTX2 Assignment
00 = PH6
01 = ETHERTX2
10 = Reserved
11 = Reserved
7:6 PH5
PH5/ETHERTX1 Assignment
00 = PH5
01 = ETHERTX1
10 = Reserved
11 = Reserved