LH79524/LH79525 User’s Guide Universal Serial Bus Device
Version 1.0 17-29
17.2.3.8 Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2)
OUTCSR2 provides further control bits for transfers through the currently-selected OUT
endpoint
.
Table 17-38. OUTCSR2 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
AUTO_CLR
ISO
USB_DMA_EN
DMA_MODE
///
RESET 0000000000000000
TYPE RORORORORORORORORWRWRWRWRRRR
ADDR
0xFFFF5000 + 0x054
(with the INDEX register set to 1 or 2)
Table 17-39. OUTCSR2 Fields
BITS NAME FUNCTION
31:8
/// Reserved Reading returns 0. Write the reset value.
7AUTO_CLR
Auto Clear This bit allows OUT_PKT_RDY to be automatically cleared
if it equals OUTMAXP. If the packet is smaller than OUTMAXP, software
must manually clear OUT_PKT_RDY.
1 = OUT_PKT_RDY is automatically programmed to 0, without any
intervention from software, each time a complete packet is read from
OUT FIFO
0 = Software must explicitly clear the OUT_PKT_RDY bit after reading
each packet
6ISO
Isochronous Enable Use this bit to enable the OUT endpoint for
isochronous transfers or to enable the OUT endpoint for bulk or interrupt
transfers.
1 = Enable the OUT endpoint for isochronous transfers
0 = Enable the OUT endpoint for bulk or interrupt transfers
5 USB_DMA_EN
USB DMA Enable Use this bit to enable DMA bulk transfers for the
OUT endpoint.
1 = The OUT FIFO is accessed via the DMA
0 = The OUT FIFO is accessed via direct Reads
4DMA_MODE
DMA Operation Mode There are two modes of DMA operation.
1 = A DMA request (but no interrupt) is generated for OUT packets of
size OUTMAXP bytes, and an interrupt is generated (but no DMA
request) for all other size packets
0 = A DMA request and interrupt is generated for all OUT packets
3:0
/// Reserved Reading returns 0. Write the reset value.
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