Sharp LH79524 - Table 15-6. CMP_CAP_CTRL0 Register; Table 15-7. CMP_CAP_CTRL0 Register Definitions; Timer 0 Compare;Capture Control Register (CMP_CAP_CTRL0)

Timers LH79524/LH79525 User’s Guide
15-8 Version 1.0
15.2.2.2 Timer 0 Compare/Capture Control Register
(CMP_CAP_CTRL0)
CMP_CAP_CTRL0 allows programming the operating modes of Timer 0.
Table 15-6. CMP_CAP_CTRL0 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD PWM TC CMP1 CMP0 CAPE CAPD CAPC CAPB CAPA
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFC4000 + 0x04
Table 15-7. CMP_CAP_CTRL0 Register Definitions
BITS NAME DESCRIPTION
31:16 ///
Reserved Reading this field returns 0. Write the reset value.
15 PWM
PWM Output Allows CTCMP0A to be used as a PWM output. This is done by
configuring this bit as well as other bits in this register. Refer to Section 15.1.3
for a complete explanation.
1 = Output pin CTCMP0A is in PWM Mode
0 = Output pin CTCMP0A is in Normal Mode and only uses the CMP0 Register
14 TC
Timer 0 Counter Operation Programs Timer 0 as a free running counter or
as an interval timer. When 1, the counter clears upon matching the T0CMP1
Register. Refer to Section 15.1.1 for a complete explanation.
1 = Clears counter when CNT0 for Timer 0 and T0CMP1 for Timer 0 match
0 = Inhibits counter clear (operates as free running counter)
13:12 CMP1
Output Value Select Timer/Counter Operation: Programs the value (when a
compare match occurs) output on the CTCMP0B pin when the CNT0 Register
matches T0CMP1.
00 = No change occurs to CTCMP0B
01 = Output 0 to CTCMP0B
10 = Output 1 to CTCMP0B
11 = Toggle the output to CTCMP0B
PWM Operation:
00 = Invalid
01 = Active HIGH PWM output polarity
10 = Active LOW PWM output polarity
11 = Invalid
IMPORTANT: CMP1 and CMP0 must be programmed to the same polarity.