Sharp LH79524 - Pending DMA Interrupts Register (INTR); Table 17-48. INTR Register; Table 17-49. INTR Fields

Universal Serial Bus Device LH79524/LH79525 User’s Guide
17-32 Version 1.0
17.2.3.13 Pending DMA Interrupts Register (INTR)
This register indicates the status of pending DMA interrupts.
Table 17-48. INTR Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
INTR6 INTR5 INTR4 INTR3 INTR2 INTR1
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFF5000 + 0x200
Table 17-49. INTR Fields
BITS NAME FUNCTION
31:6
/// Reserved Reading returns 0. Write the reset value.
5 INTR6
Channel 6 Interrupt Status
1 = Interrupt pending from DMA Channel 6
0 = No pending interrupt
4 INTR5
Channel 5 Interrupt Status
1 = Interrupt pending from DMA Channel 5
0 = No pending interrupt
3 INTR4
Channel 4 Interrupt Status
1 = Interrupt pending from DMA Channel 4
0 = No pending interrupt
2 INTR3
Channel 3 Interrupt Status
1 = Interrupt pending from DMA Channel 3
0 = No pending interrupt
1 INTR2
Channel 2 Interrupt Status
1 = Interrupt pending from DMA Channel 2
0 = No pending interrupt
0 INTR1
Channel 1 Interrupt Status
1 = Interrupt pending from DMA Channel 1
0 = No pending interrupt