Sharp LH79524 - Table 5-33. STATUS Register; Table 5-34. STATUS Fields

LH79524/LH79525 User’s Guide Direct Memory Access Controller
Version 1.0 5-17
5.2.2.10 Status Register (STATUS)
The STATUS Register provides status information about the DMA Controller interrupts.
The interrupt status bits are cleared by writing to the CLR register.
The INT[3:0] bits are the data stream interrupt flags corresponding to data stream 0
through data stream 3. A data stream sets its corresponding interrupt flag when a data
transfer is completed (a complete packet has been transferred to its destination).
The ERRORINT[3:0] bits are the Error interrupts corresponding to data stream 0 through
data stream 3. An error interrupt status is set when its corresponding data stream‘s transfer
aborts due to an AHB transfer error. When this occurs, the stream is disabled until software
sets the Enable bit again.
The Active flags indicate whether a data stream is transferring data. It is HIGH if a data
transfer is in progress. The Active flags have the same polarity as the Enable bits in the
Data Stream Control Register.
Table 5-33. STATUS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
ACTIVE3 ACTIVE2 ACTIVE1 ACTIVE0
ERRORINT3 ERRORINT2 ERRORINT1 ERRORINT0
INT3 INT2 INT1 INT0
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFE1000 + 0x0F8
Table 5-34. STATUS Fields
BIT NAME DESCRIPTION
31:12
/// Reserved Reading returns 0. Write the reset value.
11 ACTIVE3
Data Stream 3 Active/Inactive
1 = Data stream 3 is active
0 = Data stream 3 is not active
10 ACTIVE2
Data Stream 2 Active/Inactive
1 = Data stream 2 is active
0 = Data stream 2 is not active
9 ACTIVE1
Data Stream 1 Active/Inactive
1 = Data stream 1 is active
0 = Data stream 1 is not active
8 ACTIVE0
Data Stream 0 Active/Inactive
1 = Data stream 0 is active
0 = Data stream 0 is not active