Sharp LH79524 - Table 11-48. MUXCTL19 Register; Table 11-49. MUXCTL19 Fields; Multiplexing Control 19 Register (MUXCTL19)

I/O Configuration LH79524/LH79525 User’s Guide
11-34 Version 1.0
11.2.2.24 Multiplexing Control 19 Register (MUXCTL19)
The MUXCTL19 Register allows software to configure a number of LH79524/LH79525
pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525.
Table 11-48. MUXCTL19 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD PE7 PE6 PL7 PE5 PL6/D30 PE4 PE3 PL5
RESET 0000000000000000
RESET
32-Bit
0000010001000001
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0x90
Table 11-49. MUXCTL19 Fields
BIT NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:14 PE7
PE7/nWAIT/nDEOT Assignment
00 = PE7
01- = nWAIT
10 = nDEOT
11 = Reserved
13:12 PE6
PE6/LCDVEEN/LCDMOD Assignment
00 = PE6
01 = LCDVEEN
10 = LCDMOD
11 = Reserved
11:10 PL7
PL7/D31 Assignment (LH79524 Only)
00 = PL7
01 = D31
10 = Reserved
11 = Reserved
9:8 PE5
PE5/LCDVDDEN Assignment
00 = PE5
01 = LCDVDDEN
10 = Reserved
11 = Reserved
7:6 PL6
PL6/D30 Assignment (LH79524 Only)
00 = PL6
01 = D30
10 = Reserved
11 = Reserved