Sharp LH79524 - Interrupt Register for Common USB Interrupts (UIR); Table 17-12. UIR Register; Table 17-13. UIR Fields

Universal Serial Bus Device LH79524/LH79525 User’s Guide
17-14 Version 1.0
17.2.2.5 Interrupt Register for common USB interrupts (UIR)
UIR is a read-only register that indicates which USB interrupts are currently active. All
active interrupts will be cleared when this register is read.
Table 17-12. UIR Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
SOF
URINT
RESINT SUSINT
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFF5000 + 0x018
Table 17-13. UIR Fields
BITS NAME FUNCTION
31:4
/// Reserved Reading returns 0. Write the reset value.
3SOF
SOF Interrupt The USB block programs this bit to 1 at the start of each frame.
1 = Start of Frame detected
0 = Interrupt cleared
2URINT
USB RESET Interrupt The USB block programs this bit to 1 when it receives
RESET signalling from the USB Host. Software clears this interrupt by reading
this register.
1 = USB RESET Interrupt set
0 = Interrupt cleared
1 RESINT
RESUME Interrupt The USB block programs this bit to 1 when it receives
RESUME signalling while in SUSPEND mode from the USB Host. If the
RESUME is due to a USB RESET, the CPU is first interrupted with a RESUME
interrupt. Once the clocks resume and the SUSPEND condition persists for 3
ms, USB RESET Interrupt will be asserted. Software clears this interrupt by
reading this register.
1 = RESUME Interrupt set
0 = Interrupt cleared
0SUSINT
SUSPEND Interrupt The USB block programs this bit to 1 when it receives
SUSPEND signaling from the USB Host. This bit is set whenever there is no
activity for 3 ms on the bus. Thus, if the CPU does not stop the clock after the
first SUSPEND Interrupt, it will continue to be interrupted every 3 ms as long as
there is no activity on the USB bus. This interrupt is disabled by default. Soft-
ware clears this interrupt by reading this register.
1 = SUSPEND Interrupt set
0 = Interrupt cleared