Sharp LH79524 - Table 15-14. T0 Cmpn Registers; Table 15-15. T0 Cmpn Register Definitions; Timer 0 Compare Registers (T0 Cmpn)

LH79524/LH79525 User’s Guide Timers
Version 1.0 15-13
15.2.2.6 Timer 0 Compare Registers (T0CMPn)
There are two T0CMPn Registers for Timer 0. They are designated:
•T0CMP0
•T0CMP1
Each register is a 16-bit, read/write register. Contents of these registers are compared
continuously with the counter CNT0. When both register and counter values match, the
timer responds as programmed in the CMP_CAP_CTRL register.
Table 15-14. T0CMPn Registers
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD TM0CMP
RESET 1111111111111111
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR
CMP0: 0xFFFC4000 + 0x14
CMP1: 0xFFFC4000 + 0x18
Table 15-15. T0CMPn Register Definitions
BITS NAME DESCRIPTION
31:16 ///
Reserved Reading this field returns 0. Write the reset value.
15:0 TM0CMP Timer 0 Compare 16-bit compare register value.