Sharp LH79524 - Irda Low-Power Counter Register (UARTILPR); Table 16-12. UARTILPR Register; Table 16-13. UARTILPR Fields

UARTs LH79524/LH79525 User’s Guide
16-12 Version 1.0
16.3.2.4 IrDA Low-Power Counter Register (UARTILPR)
Program the UARTILPR Register with a divisor value to generate the SIR Baud Clock
signal. The UARTILPR Register is reset to 0 and must be reprogrammed with a non-zero
divisor value for use. Programming a zero value will result in no SIR Baud Clock pulses
being generated. The SIR Baud Clock is generated by dividing the UART Clock input
signal by the Low Power Divisor Value written to this register.
The Low Power Divisor value is calculated as follows:
(frequency UART Clock ÷ frequency SIR Baud Clock) – 1,
where (frequency SIR Baud Clock) is nominally 1.8432 MHz.
The divisor value written to this register must be chosen so that
1.42 MHz < SIR Baud Clock < 2.12 MHz.
The divisor value must produce a low power pulse duration of 1.41 μs - 2.11 μs (three
times the period of SIR Baud Clock).
The minimum frequency of IrLPBaud16 ensures that pulses less than one period of
UARTCLK are rejected as random noise, but that pulses greater than two periods of
UARTCLK are accepted as valid. Table 16-13 describes the bit fields in the
UARTILPR Register.
Table 16-12. UARTILPR Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// ILPDVSR
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR
UART 0: 0xFFFC0000 + 0x020
UART 1: 0xFFFC1000 + 0x020
UART 2: 0xFFFC2000 + 0x020
Table 16-13. UARTILPR Fields
BIT NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
7:0 ILPDVSR
InfraRed Low Power Divisor See text description for derivation of the
value to be programmed.