Sharp LH79524 - Table 11-14. MUXCTL5 Register; Table 11-15. MUXCTL5 Fields; Multiplexing Control 5 Register (MUXCTL5)

LH79524/LH79525 User’s Guide I/O Configuration
Version 1.0 11-9
11.2.2.7 Multiplexing Control 5 Register (MUXCTL5)
The MUXCTL5 Register allows software to configure a number of LH79524/LH79525 pins.
Table 11-14. MUXCTL5 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0x20
Table 11-15. MUXCTL5 Fields
BIT NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:14 PA1
PA1/INT3/UARTTX2/UARTIRTX2 Assignment
00 = PA1
01 = INT3
10 = UARTTX2
11 = UARTIRTX2
13:12 PA0
PA0/INT2/UARTRX2/UARTIRRX2 Assignment
00 = PA0
01 = INT2
10 = UARTRX2
11 = UARTIRRX2
11:10 PB7
PB7/INT1/UARTTX0/UARTIRTX0 Assignment
00 = PB7
01 = INT1
10 = UARTTX0
11 = UARTIRTX0
9:8 PB6
PB6/INT0/UARTRX0/UARTIRRX0 Assignment
00 = PB6
01 = INT0
10 = UARTRX0
11 = UARTIRRX0
7:6 PB5
PB5/SSPTX/UARTTX1/UARTIRTX1 Assignment
00 = PB5
01 = SSPTX
10 = UARTTX1
11 = UARTIRTX1
5:4 PB4
PB4/SSPRX/UARTRX1/UARTIRRX1 Assignment
00 = PB4
01 = SSPRX
10 = UARTRX1
11 = UARTIRRX1
3:2 PB3
PB3/SSPCLK Assignment
00 = PB3
01 = SSPCLK
10 = Reserved
11 = Reserved
1:0 PB2
PB2/SSPFRM Assignment
00 = PB2
01 = SSPFRM
10 = Reserved
11 = Reserved