Sharp LH79524 - Table 11-10. MUXCTL4 Register; Table 11-11. MUXCTL4 Fields; Multiplexing Control 4 Register (MUXCTL4)

LH79524/LH79525 User’s Guide I/O Configuration
Version 1.0 11-7
11.2.2.5 Multiplexing Control 4 Register (MUXCTL4)
The MUXCTL4 Register allows software to configure a number of LH79524/LH79525 pins.
Table 11-10. MUXCTL4 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// PA7 PA6 PA5 PA4 PA3 PA2
RESET 0000000000000000
RW RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0x18
Table 11-11. MUXCTL4 Fields
BIT NAME DESCRIPTION
31:12 /// Reserved Reading returns 0. Write the reset value.
11:10 PA7
PA7/CTCAP2B/CTCMP2B/SCL Assignment
00 = PA7
01 = CTCAP2B
10 = CTCMP2B
11 = SCL
9:8 PA6
PA6/CTCAP2A/CTCMP2A/SDA Assignment
00 = PA6
01 = CTCAP2A
10 = CTCMP2A
11 = SDA
7:6 PA5
PA5/CTCAP1B/CTCMP1B Assignment
00 = PA5
01 = CTCAP1B
10 = CTCMP1B
11 = Reserved
5:4 PA4
PA4/CTCAP1A/CTCMP1A Assignment
00 = PA4
01 = CTCAP1A
10 = CTCMP1A
11 = Reserved
3:2 PA3
PA3/CTCAP0B/CTCMP0B Assignment
00 = PA3
01 = CTCAP0B
10 = CTCMP0B
11 = Reserved
1:0 PA2
PA2/CTCAP0A/CTCMP0A Assignment
00 = PA2
01 = CTCAP0A
10 = CTCMP0A
11 = Reserved