Sharp LH79524 - Lower Panel Frame Buffer Base Address Register (LPBASE); Table 4-22. LPBASE Register; Table 4-23. LPBASE Register Fields

LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller
Version 1.0 4-27
4.5.3.5 Lower Panel Frame Buffer Base Address Register (LPBASE)
The LPBASE Register is one of two Color LCD DMA Base Address Registers (the other is
UPBASE, described in Section 4.5.3.4). Together with UPBASE, this Read/Write register
programs the base address of the frame buffer.
LPBASE is used for the lower panel of dual-panel STN displays. UPBASE must be initial-
ized (and LPBASE for dual panels) before enabling the CLCDC. Optionally, the value can
be changed mid-frame to allow double-buffered video displays to be created. These reg-
isters are copied to the corresponding current registers at each LCD vertical synchroniza-
tion. This event causes the BUI bit and an optional interrupt to be generated. The BUI bit
indicates that it is safe to update both the UPBASE and LPBASE Registers. The interrupt
can be used to reprogram the base address when generating double-buffered video.
Table 4-22. LPBASE Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD LCDLPBASE
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD LCDLPBASE ///
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RO RO
ADDR 0xFFFF4000 + 0x14
Table 4-23. LPBASE Register Fields
BIT NAME DESCRIPTION
31:2 LCDLPBASE
LCD Lower Panel Base Address This is the start address of the
lower panel frame data in memory and is word-aligned.
1:0 /// Reserved Reading returns 0. Write the reset value.