Sharp LH79524 - Table 14-17. MIS Register; Table 14-18. MIS Fields; Masked Interrupt Status Register (MIS)

Synchronous Serial Port LH79524/LH79525 User’s Guide
14-18 Version 1.0
14.2.2.8 Masked Interrupt Status Register (MIS)
MIS is the Masked Interrupt Status Register. When read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
Table 14-17. MIS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
TXMIS
RXMIS
RTMIS
RORMIS
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC6000 + 0x01C
Table 14-18. MIS Fields
BITS NAME DESCRIPTION
31:4 /// Reserved Reading returns 0. Write the reset value.
3TXMIS
Transmit FIFO Masked Interrupt Status Gives the Transmit FIFO masked
interrupt state.
1 = Interrupt asserted
0 = Interrupt not asserted or is masked
2RXMIS
Receive FIFO Masked Interrupt Status Gives the Receive FIFO masked
interrupt state.
1 = Interrupt asserted
0 = Interrupt not asserted or is masked
1RTMIS
Receive Timeout Masked Interrupt Status Gives the Receive Timeout
masked interrupt state.
1 = Interrupt asserted
0 = Interrupt not asserted or is masked
0RORMIS
Receive Overrun Masked Interrupt Status Gives the Receive Overrun
masked interrupt state.
1 = Interrupt asserted
0 = Interrupt not asserted or is masked