Sharp LH79524 - Masked Interrupt Status Register (MIS); Table 10-11. MIS Register; Table 10-12. MIS Register Definitions

LH79524/LH79525 User’s Guide I
2
S Converter
Version 1.0 10-19
10.2.2.5 Masked Interrupt Status Register (MIS)
This register provides the current masked status value of the corresponding interrupt.
Writing has no effect; all bits are read only. For each bit, 1 = TRUE and 0 = FALSE.
Table 10-11. MIS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
SSPPEMIS
ECPEMIS
TXUEMIS
TXMIS
RXMIS
RTMIS
RORMIS
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC8000 + 0x010
Table 10-12. MIS Register Definitions
BITS NAME DESCRIPTION
31:7 /// Reserved Reading returns 0. Write the reset value.
6 SSPPEMIS
SSP Protocol Error masked interrupt status Gives the Master Mode
Protocol Error masked interrupt state.
5 ECPEMIS
External Codec Protocol Error masked interrupt status Gives the
Slave Mode Protocol Error masked interrupt state
4TXUEMIS
Transmit Underrun Error masked interrupt status Gives the Transmit
Underrun Error masked interrupt state.
3TXMIS
Transmit FIFO masked interrupt status (from SSP MIS:TXMIS bit) Gives
the Transmit FIFO masked interrupt state.
2RXMIS
Receive FIFO masked interrupt status (from SSP MIS:RXMIS bit) Gives
the Receive FIFO masked interrupt state.
1RTMIS
Receive timeout masked interrupt status (from SSP MIS:RTMIS bit)
Gives the Receive Timeout masked interrupt state.
0RORMIS
Receive overrun masked interrupt status (from SSP MIS:RORMIS bit)
Gives the Receive Overrun masked interrupt state.