UARTs LH79524/LH79525 User’s Guide
16-10 Version 1.0
Table 16-8 and Table 16-9 describe the UARTRSR/UARTECR Register for Read operations.
Table 16-8. UARTRSR/UARTECR Register (Read Operations)
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 00000000000000 0 0
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// OE BE PEAR FE
RESET 00000000000000 0 0
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR
UART 0: 0xFFFC0000 + 0x004
UART 1: 0xFFFC1000 + 0x004
UART 2: 0xFFFC2000 + 0x004
Table 16-9. UARTRSR/UARTECR Fields (Read Operations)
BITS NAME DESCRIPTION
31:4 /// Reserved Reading returns 0. Write the reset value.
3OE
Data Overrun Error This bit signifies when a data overrun has occurred.
1 = Data is received and the FIFO is already full
0 = Cleared to 0 by a write to the UARTECR Register. The FIFO contents remain
valid since no further data is written when the FIFO is full, only the contents
of the shift register are overwritten. The CPU must now read the data in order
to empty the FIFO.
2BE
Break Error In FIFO Mode, this error is associated with the character at the top
of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO.
The next character is only enabled after the receive data input goes to a 1 (Idle
state) and the next valid Start bit is received.
1 = A break condition was detected, indicating that the received data input was
held LOW for longer than a full-word transmission time (defined as Start,
data, parity, and Stop bits)
0 = This bit is cleared to 0 after a write to the UARTECR Register
1 PEAR
Parity Error/Address Received See Table 16-5. This bit is cleared to 0 by a
write to UARTECR.
0FE
Framing Error This bit indicates a Framing Error has occurred.
1 = The received character did not have a valid Stop bit (valid Stop bit is 1)
0 = This bit is cleared to 0 by a write to the UARTECR Register
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