Sharp LH79524 - Raw Interrupt Status Register (STATUS); Table 4-28. STATUS Register; Table 4-29. STATUS Fields

Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide
4-32 Version 1.0
4.5.3.8 Raw Interrupt Status Register (STATUS)
STATUS is the Raw Interrupt Status Register. The status of the interrupts without masking
applied is contained in this register.
Table 4-28. STATUS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
MBEI
VCI BUI FUI ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFF4000 + 0x20
Table 4-29. STATUS Fields
BIT NAME DESCRIPTION
31:5 /// Reserved Reading returns 0. Write the reset value.
4 MBEI
AMBA AHB Master Bus Error Status Indicates that the CLCDC AHB master
has encountered a bus error response from a slave.
1 = Interrupt asserted
0 = No interrupt
3VCI
Vertical Compare Set to 1 when one of the four vertical regions selected in the
CONTROL register is reached.
1 = Interrupt asserted
0 = No interrupt
2BUI
LCD Next Base Address Update Mode dependent; set to 1 when the Current
Base Address registers have been successfully updated with the data from Next
Address registers. Signifies that a new Next Address can be loaded if double buff-
ering is in use.
1 = Interrupt asserted
0 = No interrupt
1FUI
FIFO Underflow Set to 1 when either the upper or lower DMA FIFOs have been
accessed when empty, resulting in an underflow condition
1 = Interrupt asserted
0 = No interrupt
0///Reserved Reading returns 0. Write the reset value.