Sharp LH79524 - Interrupt Disable Register (DISABLE); Table 6-24. DISABLE Register; Table 6-25. DISABLE Fields

LH79524/LH79525 User’s Guide Ethernet MAC Controller
Version 1.0 6-33
6.3.2.10 Interrupt Disable Register (DISABLE)
This register is used to disable individual interrupts. All interrupts are disabled following a
reset. Writing a 1 to the relevant bit location disables that particular interrupt. This register
is write only.
Table 6-24. DISABLE Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
PAUSETMZEROIDIS
PAUSEFRRXIDIS
NOTOKIDIS
RECOVERRUNIDIS
///
TXCOMPIDIS
TXBUFEXHIDIS
RETRYLMTEXIDIS
TXBUFUNDERIDIS
TXUSEDBITIDIS
RXUSEDBITIDIS
RXCOMPIDIS
MNGDONEIDIS
RESET 00––––––––––––––
TYPE RO RO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
ADDR 0xFFFC7000 + 0x2C
Table 6-25. DISABLE Fields
BITS NAME FUNCTION
31:14 /// Reserved Reading returns 0. Write the reset value.
13 PAUSETMZEROIDIS Disable Pause Time Zero Interrupt
12 PAUSEFRRXIDIS Disable Pause Frame Received Interrupt
11 NOTOKIDIS Disable Response ‘Not OK’ Interrupt
10 RECOVERRUNIDIS Disable Receive Overrun Interrupt
9:8 /// Reserved Reading returns 0. Write the reset value.
7 TXCOMPIDIS Disable Transmit Complete Interrupt
6 TXBUFEXHIDIS Disable Transmit Buffers Exhausted In Mid-Frame Interrupt
5 RETRYLMTEXIDIS Disable Retry Limit Exceeded Interrupt
4 TXBUFUNDERIDIS Disable Transmit Buffer Underrun Interrupt
3 TXUSEDBITIDIS Disable Transmit Used Bit Read Interrupt
2 RXUSEDBITIDIS Disable Receive Used Bit Read Interrupt
1 RXCOMPIDIS Disable Receive Complete Interrupt
0 MNGDONEIDIS Disable Management Done Interrupt