Sharp LH79524 - Register Descriptions; Table 2-2. HW Register; Table 2-3. HW Fields

LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector
Version 1.0 2-11
2.2.2 Register Descriptions
2.2.2.1 High Word Register (HW)
HW is the High Word Register. This Read Only status register shows the contents of the
current conversion’s high word in the control bank. There is a one-to-one correspondence
between the contents of the control bank high word and the contents of this register for the
current conversion in progress.
Table 2-2. HW Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD SETTIME INP INM REFP
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC3000 + 0x00
Table 2-3. HW Fields
BITS NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:7 SETTIME
Number of Clock Cycles Specifies the number of clock cycles that the ADC
allows for the input signal to settle to within required accuracy before beginning
conversion. Used with bits [10:8] of the PC Register to set the acquire time in
clock cycles (see Section 2.2.2.5).
For example, if Frequency In (ƒIN) = 2 MHz (500 ns period):
PC[10:8] = 010 (i.e., divide ƒIN by 4)
HW[15:6] = 000100000 (i.e., 32 cycles)
Therefore, acquire time is 500 ns × 4 × 32 = 64 μs
6:3 INP
In+ Mux Determines the signal connected to the positive input of the ADC.
See Table 2-4.
2INM
In- Mux Determines the signal connected to the negative input of the ADC.
1 = GND
0 = Ref- (output of the Ref- Mux)
1:0 REFP
Ref+ Mux Determines the signal connected to the positive reference of the ADC.
00 = VREF+ (positive terminal of the internal bandgap reference)
01 = AN0 (UL/X+)
10 = AN2 (LL/ Y+)
11 = AN8