Sharp LH79524 - Dynamic Memory Read Configuration Register (DYNMRCON); Table 7-21. DYNMRCON Register; Table 7-22. DYNMRCON Fields

LH79524/LH79525 User’s Guide External Memory Controller
Version 1.0 7-35
7.5.2.6 Dynamic Memory Read Configuration Register (DYNMRCON)
This register allows configuration of the dynamic memory Read strategy. This register
should only be modified during initialization. This register provides the Read strategy for
all four dynamic memory Chip Select signals. The DYNMRCON resets to 0x00, which is
invalid. Therefore, this register must be programmed to 0x01 during initialization if the
SDRAM controller is used.
Table 7-21. DYNMRCON Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// RDS
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW
ADDR 0xFFFF1000 + 0x028
Table 7-22. DYNMRCON Fields
BITS NAME FUNCTION
31:2 /// Reserved Reading returns 0. Write the reset value.
1:0 RDS
Read Data Strategy This field selects the Read strategy.
00 = Reserved
01 = Command Delayed Strategy (Clock Out not delayed; command delayed)
10 = Reserved
11 = Reserved