Sharp LH79524 - Table 11-26. MUXCTL10 Register; Table 11-27. MUXCTL10 Fields; Multiplexing Control 10 Register (MUXCTL10)

I/O Configuration LH79524/LH79525 User’s Guide
11-18 Version 1.0
11.2.2.13 Multiplexing Control 10 Register (MUXCTL10)
The MUXCTL10 Register allows software to configure a number of LH79524/LH79525
pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525.
Table 11-26. MUXCTL10 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD PN3 PN2 PD7 PK7 PD6 PK6 PD5 PK5
LH79525
RESET
0000010001000100
LH79524
RESET
0101010101010101
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0x48
Table 11-27. MUXCTL10 Fields
BIT NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:14
PN3
PN3/D25 Assignment (LH79524 Only)
00 = PN3
01 = D25
10 = Reserved
11 = Reserved
13:12
PN2
PN2/D24 Assignment (LH79524 Only)
00 = PN2
01 = D24
10 = Reserved
11 = Reserved
11:10 PD7
PD7/D15 Assignment
00 = PD7
01 = D15
10 = Reserved
11 = Reserved
9:8 PK7
PK7/D23 Assignment (LH79524 Only)
00 = PK7
01 = D23
10 = Reserved
11 = Reserved
7:6 PD6
PD6/D14 Assignment
00 = PD6
01 = D14
10 = Reserved
11 = Reserved