Sharp LH79524 - Table 14-15. RIS Register; Table 14-16. RIS Fields; Raw Interrupt Status Register (RIS)

LH79524/LH79525 User’s Guide Synchronous Serial Port
Version 1.0 14-17
14.2.2.7 Raw Interrupt Status Register (RIS)
This register provides the current raw status value of the corresponding interrupt prior to
masking. A write has no effect.
Table 14-15. RIS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
TXRIS
RXRIS
RTRIS
RORRIS
RESET 0000000000001000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC6000 + 0x018
Table 14-16. RIS Fields
BITS NAME DESCRIPTION
31:4 /// Reserved Reading returns 0. Write the reset value.
3TXRIS
Transmit FIFO Raw Interrupt Status Gives the raw interrupt state (pri-
or to masking) of the Transmit FIFO interrupt.
1 = Interrupt asserted
0 = Interrupt not asserted
2RXRIS
Receive FIFO Raw Interrupt Status Gives the raw interrupt state (pri-
or to masking) of the Receive FIFO interrupt.
1 = Interrupt asserted
0 = Interrupt not asserted
1RTRIS
Receive Timeout Raw Interrupt Status Gives the raw interrupt state
(prior to masking) of the Receive Timeout interrupt.
1 = Interrupt asserted
0 = Interrupt not asserted
0RORRIS
Receive Overrun Raw Interrupt Status Gives the raw interrupt state
(prior to masking) of the Receive Overrun interrupt.
1 = Interrupt asserted
0 = Interrupt not asserted