Sharp LH79524 - Table 6-12. TXSTATUS Register; Table 6-13. TXSTATUS Fields; Transmit Status Register (TXSTATUS)

LH79524/LH79525 User’s Guide Ethernet MAC Controller
Version 1.0 6-25
6.3.2.4 Transmit Status Register (TXSTATUS)
This register provides transmit status details. Individual bits may be cleared by writing 1 to
them. It is not possible to program a bit to 1 by writing to the register.
Table 6-12. TXSTATUS Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
TXUNDER
TXCOMPLETE
BUFEX
TXGO
RETRYLIMIT
COLLISION
USEDBIT
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RW RW RW RO RW RW RW
ADDR 0xFFFC7000 + 0x14
Table 6-13. TXSTATUS Fields
BITS NAME FUNCTION
31:7 /// Reserved Reading returns 0. Write the reset value.
6 TXUNDER
Transmit Underrun This bit shows when transmit DMA was not able
to read data from the buffer in system memory. The cause can be that
the AHB or ASB bus was not granted in time, a ‘Not OK’ response was
returned, a zero length buffer was read, or because a Used bit was read
midway through frame transmission. If this happens, the transmitter forc-
es a bad CRC and the Transmit Error (ETHERTXER) pin HIGH.
Read:
1 = DMA Unable to read data from memory
0 = Normal operation
Write:
1 = Reset bit to 0
0 = No effect
5 TXCOMPLETE
Transmit Complete Advises when a frame has been transmitted.
Read:
1 = Frame transmission complete
0 = Frame transmission not complete
Write:
1 = Reset bit to 0
0 = No effect