Sharp LH79524 - Dynamic Memory Data-In to Active Time Register (DIACTIVE); Table 7-31. DIACTIVE Register; Table 7-32. DIACTIVE Fields

External Memory Controller LH79524/LH79525 User’s Guide
7-40 Version 1.0
7.5.2.11 Dynamic Memory Data-In to Active Time Register (DIACTIVE)
The Dynamic Memory Data-In to Active Time Register enables programming the Data-in
to Active Command time, tDAL. This value is normally found in SDRAM data sheets as
tDAL, or tAPW.
This register must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
Table 7-31. DIACTIVE Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// tDAL
RESET 0000000000001111
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
ADDR 0xFFFF1000 + 0x040
Table 7-32. DIACTIVE Fields
BITS NAME FUNCTION
31:4 /// Reserved Reading returns 0. Write the reset value.
3:0 tDAL
Data-In to Active Command Time
Time = (tDAL) External Memory Clock periods