Sharp LH79524 - Static Memory Turn Around Delay Registers (Sturnx); Table 7-64. Sturnx Register; Table 7-65. Sturnx Fields

LH79524/LH79525 User’s Guide External Memory Controller
Version 1.0 7-59
7.5.2.27 Static Memory Turn Around Delay Registers (STURNx)
The Static Memory Turn Around Delay Registers enable programming the number of bus
turnaround cycles.
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
To prevent bus contention on the external memory data bus, the BTC field controls the
number of bus turnaround cycles added between static memory read and write accesses.
The BTC field also controls the number of turnaround cycles between static memory and
dynamic memory accesses.
Table 7-64. STURNx Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// BTC
RESET 0000000000001111
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
ADDR
0xFFFF1000 + 0x218 for STURN0
0xFFFF1000 + 0x238 for STURN1
0xFFFF1000 + 0x258 for STURN2
0xFFFF1000 + 0x278 for STURN3
Table 7-65. STURNx Fields
BITS NAME FUNCTION
31:4 /// Reserved Reading returns 0. Write the reset value.
3:0 BTC
Bus Turnaround Cycles SRAM Wait State time for Write accesses after the
first Read:
Bus Turnaround Cycles = (BTC + 1) HCLK cycles