Sharp LH79524 - Static Memory Read Delay Registers (Swaitrdx); Table 7-58. Swaitrdx Register; Table 7-59. Swaitrdx Fields

External Memory Controller LH79524/LH79525 User’s Guide
7-56 Version 1.0
7.5.2.24 Static Memory Read Delay Registers (SWAITRDx)
The Static Memory Read Delay Registers enable programming Read cycle wait states. A
complete description of programming this register appears in Section 7.2.4.1.1.
The total Read cycle time is the total time that the address is valid. During this time, several
parameters are programmable. In the following equations, ‘D’ represents the SWAITOENx
register, ‘E’ represents the SWAITRDx register, and ‘C’ represents the address hold time.
In general, Read wait states can be derived from the following equation:
tRC (Read cycle time) = tD1 + tD2 + ... tDn + tE0 + tE1 + ... tEn + C, where the length of
each term is one HCLK period, and ‘n’ is the value programmed in the respective register.
The minimum value for the equation is tRC = tE0 + C, and is therefore the zero wait
state timing.
Thus, Read wait states can be programmed using the appropriate mix of nOE extension
(programmed in SWAITRDx) with nOE assertion delay (programmed in SWAITOENx).
These registers must only be modified during system initialization, or when there are no
current or outstanding transactions. Software can ensure that there are no current or out-
standing transactions by waiting until the memory controller is idle, then entering Low-
Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0). When
in these two modes, external memory access is not allowed, ensuring that changing
parameters will not corrupt external data. Low-Power Mode automatically refreshes
SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
Table 7-58. SWAITRDx Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// WAITRD
RESET 0000000000011111
TYPE RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW
ADDR
0xFFFF1000 + 0x20C for SWAITRD0
0xFFFF1000 + 0x22C for SWAITRD1
0xFFFF1000 + 0x24C for SWAITRD2
0xFFFF1000 + 0x26C for SWAITRD3
Table 7-59. SWAITRDx Fields
BITS NAME FUNCTION
31:5 /// Reserved Reading returns 0. Write the reset value.
4:0 WAITRD
Read Access Delay Non-page mode Read or Asynchronous Page Mode
Read, delay first read only:
Delay = (n + 1) HCLK cycles