Sharp LH79524 - Multiplexing Control 21 Register (MUXCTL21); Table 11-56. MUXCTL21 Register; Table 11-57. MUXCTL21 Fields

I/O Configuration LH79524/LH79525 User’s Guide
11-42 Version 1.0
11.2.2.28 Multiplexing Control 21 Register (MUXCTL21)
The MUXCTL21 Register allows software to configure a number of LH79524/LH79525
pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525.
Table 11-56. MUXCTL21 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// PF5 PL3 PF4 PL2 PF3 PF2
RESET 0000000000000000
RW RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0xA0
Table 11-57. MUXCTL21 Fields
BIT NAME DESCRIPTION
31:12 /// Reserved Reading returns 0. Write the reset value.
11:10 PF5
PF5/LCDVD11 Assignment
00 = PF5
01 = LCDVD11
10 = Reserved
11 = Reserved
9:8 PL3
PL3/LCDVD13 Assignment (LH79524 Only)
00 = PL3
01 = LCDVD13
10 = Reserved
11 = Reserved
7:6 PF4
PF4/LCDVD10 Assignment
00 = PF4
01 = LCDVD10
10 = Reserved
11 = Reserved
5:4 PL2
PL2/LCDVD12 Assignment (LH79524 Only)
00 = PL2
01 = LCDVD12
10 = Reserved
11 = Reserved
3:2 PF3
PF3/LCDVD9 Assignment
00 = PF3
01 = LCDVD9
10 = Reserved
11 = Reserved
1:0 PF2
PF2/LCDVD8 Assignment
00 = PF2
01 = LCDVD8
10 = Reserved
11 = Reserved