Sharp LH79524 - Reset Status Clear Register (RSTSTATUSCLR); Table 13-14. RSTSTATUSCLR Register; Table 13-15. RSTSTATUSCLR Fields

Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide
13-16 Version 1.0
13.2.2.6 Reset Status Clear Register (RSTSTATUSCLR)
This Write Only register clears the two Reset Status flags in the RSTSTATUS register.
Writing 1 to this register causes the corresponding bit in the RSTSTATUS to be cleared to
0. Writing 0 has no effect on the corresponding bit in the Reset Status register. Writing to
reserved bits has no effect on the RCPC.
Table 13-14. RSTSTATUSCLR Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET ————————————————
RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
TOCLR
EXTCLR
RESET ————————————————
RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
ADDR 0xFFFE2000 + 0x14
Table 13-15. RSTSTATUSCLR Fields
BITS NAME DESCRIPTION
31:2 /// Reserved Reads undefined. Write 0 only.
1TOCLR
Clear WDT Timeout Write 1 to clear the WDTO status bit. Reads return
unpredictable results.
1 = Clears WDTO bit in the RSTSTATUS Register to 0
0 = No effect
0 EXTCLR
Clear External Reset Write 1 to clear the EXT status bit. Reads return
unpredictable results.
1 = Clears EXT bit in the RSTSTATUS Register to 0
0 = No effect