Sharp LH79524 - Multiplexing Control 20 Register (MUXCTL20); Table 11-52. MUXCTL20 Register; Table 11-53. MUXCTL20 Fields

I/O Configuration LH79524/LH79525 User’s Guide
11-38 Version 1.0
11.2.2.26 Multiplexing Control 20 Register (MUXCTL20)
The MUXCTL20 Register allows software to configure a number of LH79524/LH79525
pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525.
Table 11-52. MUXCTL20 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD PE2 PL4 PE1 PN1 PE0 PN0 PF7 PF6
LH79525
RESET
0000000000000000
LH79524
RESET
0001000100010000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE5000 + 0x98
Table 11-53. MUXCTL20 Fields
BIT NAME DESCRIPTION
31:16 /// Reserved Reading returns 0. Write the reset value.
15:14 PE2
PE2/LCDPS Assignment
00 = PE2
01 = LCDPS
10 = Reserved
11 = Reserved
13:12 PL4
PL4/D28 Assignment (LH79524 Only)
00 = PL4
01 = D28
10 = Reserved
11 = Reserved
11:10 PE1
PE1/LCDDCLK Assignment
00 = PE1
01 = LCDDCLK
10 = Reserved
11 = Reserved
9:8 PN1
PN1/D27 Assignment (LH79524 Only)
00 = PN1
01 = D27
10 = Reserved
11 = Reserved
7:6 PE0
PE0/LCDLP/LCDHRLP Assignment
00 = PE0
01 = LCDLP
10 = LCDHRLP
11 = Reserved