Sharp LH79524 - Table 4-49. ALITIMING2 Register; Table 4-50. ALITIMING2 Fields; Timing Delay Register 2 (ALITIMING2)

LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller
Version 1.0 4-41
4.5.6.4 Timing Delay Register 2 (ALITIMING2)
The ALITIMING2 Register is used for various delay values for output signals. All delays
are specified in number of LCD clock (LCDDCLK) periods.
Table 4-49. ALITIMING2 Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD SPLDEL PS2CLS2
RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFE4000 + 0x00C
Table 4-50. ALITIMING2 Fields
BITS NAME DESCRIPTION
31:16
/// Reserved Reading returns 0. Write the reset value.
15:9
SPLDEL
LCDSPL Delay Controls the delay in LCDDCLK periods of the LCDSPL sig-
nal during vertical front and back porches. This field must be programmed to
a value greater than the sum of (TIMING0:HSW + TIMING0:HBP).
SPLDEL = (LCDDCLK periods) – 1
8:0 PS2CLS2
LCDSPL and LCDCLS Delay 2 Controls the delay in LCDDCLK periods
from the first rising edge of the LCDSPL signal to the trailing edge of the
LCDCLS and LCDPS signals. The value of this field must be greater than 0.
PS2CLS2 = (LCDDCLK periods) – 1