Sharp LH79524 - Dynamic Memory Active Bank a to Active Bank B Time Register (DYNACTIVEAB); Table 7-41. DYNACTIVEAB Register; Table 7-42. DYNACTIVEAB Fields

LH79524/LH79525 User’s Guide External Memory Controller
Version 1.0 7-45
7.5.2.16 Dynamic Memory Active Bank A to Active Bank B
Time Register (DYNACTIVEAB)
The Dynamic Memory Active Bank A to Active Bank B Time Register programs the active
bank A to active bank B latency, tRRD. This value is normally found in SDRAM data sheets
as tRRD.
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
Table 7-41. DYNACTIVEAB Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// tRRD
RESET 0000000000001111
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
ADDR 0xFFFF1000 + 0x054
Table 7-42. DYNACTIVEAB Fields
BITS NAME FUNCTION
31:4 /// Reserved Reading returns 0. Write the reset value.
3:0 tRRD
Active Bank A to Active Bank B Latency
Latency = (tRRD + 1) External Memory Clock periods