Sharp LH79524 - Figure 1-1. LH79524;LH79525 Block Diagram

Overview LH79524/LH79525 User’s Guide
1-2 Version 1.0
Figure 1-1. LH79524/LH79525 Block Diagram
LH79525-1
OSCILLATOR,
PLL(2), POWER
MANAGEMENT, and
RESET CONTROL
VECTORED
INTERRUPT
CONTROLLER
CONDITIONED
EXTERNAL
INTERRUPTS
INTERNAL
INTERRUPTS
CACHE
INTERNAL
16KB SRAM
ETHERNET
MAC
LINEAR
REGULATOR
TEST
SUPPORT
10 - 20 MHz 32.768 kHz
REAL TIME
CLOCK
COLOR
LCD
CONTROLLER
EXTERNAL
MEMORY
CONTROLLER
ADVANCED
PERIPHERAL
BUS BRIDGE
ADVANCED HIGH
PERFORMANCE
BUS (AHB)
ADVANCED
PERPHERAL
BUS (APB)
BOOT
ROM
ADVANCED
LCD
INTERFACE
4 CHANNEL
DMA
CONTROLLER
BOOT
CONTROLLER
GENERAL
PURPOSE I/O
I/O
CONFIGURATION
SYNCHRONOUS
SERIAL PORT
COUNTER/
TIMER (3)
WATCHDOG
TIMER
I
2
C
10 CHANNEL
10-BIT ADC
(WITH TSC and
BROWNOUT
DETECTOR)
USB
DEVICE
16550
UART (3) w/SIR
ARM720T
SSP - I
2
S
CONVERTER
(WITH CODEC
INTERFACE)
LH79524/ LH79525