Sharp LH79524 - Interrupt Enable Register (ENABLE); Table 6-22. ENABLE Register; Table 6-23. ENABLE Fields

Ethernet MAC Controller LH79524/LH79525 User’s Guide
6-32 Version 1.0
6.3.2.9 Interrupt Enable Register (ENABLE)
At reset all interrupts are disabled. Writing a 1 to the relevant bit location enables the
required interrupt. This register is write only
.
Table 6-22. ENABLE Register
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ///
PAUSETMZEROIEN
PAUSEFRRXIEN
NOTOKIEN
RECOVERRUNIEN
///
TXCOMPIEN
TXBUFEXHIEN
RETRYLMTEXIEN
TXBUFUNDERIEN
TXUSEDBITIEN
RXUSEDBITIEN
RXCOMPIEN
MNGDONEIEN
RESET 00––––––––––––––
TYPE RO RO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
ADDR 0xFFFC7000 + 0x28
Table 6-23. ENABLE Fields
BITS NAME FUNCTION
31:14 /// Reserved Reading returns 0. Write the reset value.
13 PAUSETMZEROIEN Pause Time Zero Interrupt Enable
12 PAUSEFRRXIEN Pause Frame Received Interrupt Enable
11 NOTOKIEN Response Not OK Interrupt Enable
10 RECOVERRUNIEN Receive Overrun Interrupt Enable
9:8 /// Reserved Reading returns 0. Write the reset value.
7 TXCOMPIEN Transmit Complete Interrupt Enable
6 TXBUFEXHIEN Transmit Buffers Exhausted In Mid-frame Interrupt Enable
5 RETRYLMTEXIEN Retry Limit Exceeded Interrupt Enable
4 TXBUFUNDERIEN Transmit Buffer Underrun Interrupt Enable
3 TXUSEDBITIEN Transmit Used Bit Read Interrupt Enable
2 RXUSEDBITIEN Receive Used Bit Read Interrupt Enable
1 RXCOMPIEN Receive Complete Interrupt Enable
0 MNGDONEIEN Management Done Interrupt Enable