Universal Serial Bus Device LH79524/LH79525 User’s Guide
17-22 Version 1.0
3 DATA_END
Data End Software programs this bit to 1:
• After loading the last packet of data into the FIFO, at the same
time IN_PKT_RDY is set
• While it clears OUT_PKT_RDY after unloading the last packet of
data. For a zero-length data phase, when it clears
OUT_PKT_RDY and sets IN_PKT_RDY.
1 = Last packet loaded to FIFO
0 = Last packet unloaded from FIFO
2 SENT_STALL
Sent Stall Handshake The USB device programs this bit to 1 if the
USB Host ends a control transaction due to a protocol violation. An
interrupt is generated when this bit is set. Software must clear this bit
by writing a 0.
1 = Protocol violation
0 = Normal operation
1 IN_PKT_RDY
IN Packet Ready Software programs this bit to 1 after writing a
packet of data into ENDPOINT 0 FIFO. The USB block programs
this bit to 0 when the USB Host signals that the packet has been suc-
cessfully received at the Host. An interrupt is generated when the
USB Host clears this bit, so software can load the next packet. For a
zero-length data phase, software programs IN_PKT_RDY and
DATA_END (bit 3) to 1 at the same time.
1 = Data packet written to ENDPOINT 0 FIFO
0 = Data packet successfully sent to USB host
0 OUT_PKT_RDY
OUT Packet Ready This is a Read Only bit. The USB programs
this bit to 1 once valid data from the packet is written to the FIFO. An
interrupt is generated when the USB sets this bit. Software programs
this bit to 0 writing a 1 to the CLR_OUT bit (bit 6).
1 = Valid data from packet has been written to the OUT FIFO
0 = No pending data from packet
Table 17-29. CSR0 Fields (Cont’d)
BITS NAME FUNCTION
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