Sharp LH79524 - Page 22

LH79524/LH79252 User’s Guide
Version 1.0 xxi
Table 4-27. CTRL Fields ..........................................................................................4-30
Table 4-28. STATUS Register..................................................................................4-32
Table 4-29. STATUS Fields .....................................................................................4-32
Table 4-30. INTERRUPT Register ...........................................................................4-33
Table 4-31. INTERRUPT Fields...............................................................................4-33
Table 4-32. INTCLR Register...................................................................................4-34
Table 4-33. INTCLR Fields.......................................................................................4-34
Table 4-34. UPCURR Register ................................................................................4-35
Table 4-35. UPCURR Fields ....................................................................................4-35
Table 4-36. LPCURR Register.................................................................................4-35
Table 4-37. LCDLPCURR Fields..............................................................................4-35
Table 4-38. PALETTE Register (LH79525 with 12-Bit CLCDC)...............................4-36
Table 4-39. PALETTE Fields (LH79525 with 12-Bit CLCDC) ..................................4-36
Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC)...............................4-37
Table 4-41. PALETTE Fields (LH79524 with 16-Bit CLCDC) ..................................4-37
Table 4-42. ALI Register Summary..........................................................................4-38
Table 4-43. ALISETUP Register ..............................................................................4-38
Table 4-44. ALISETUP Fields ..................................................................................4-38
Table 4-45. ALICTRL Register.................................................................................4-39
Table 4-46. ALICTRL Fields.....................................................................................4-39
Table 4-47. ALITIMING1 Register............................................................................4-40
Table 4-48. ALITIMING1 Fields................................................................................4-40
Table 4-49. ALITIMING2 Register............................................................................4-41
Table 4-50. ALITIMING2 Fields................................................................................4-41
Chapter 5 – Direct Memory Access Controller
Table 5-1. DMA Controller Stream Assignments and Request Priority......................5-1
Table 5-2. DMA Memory Map ....................................................................................5-5
Table 5-3. DMA Data Stream Register Summary
(One Set of Registers for Each of the Four Data Streams in Table 5-2)................5-5
Table 5-4. SOURCELO Register................................................................................5-6
Table 5-5. SOURCELO Fields ...................................................................................5-6
Table 5-6. SOURCEHI Register.................................................................................5-6
Table 5-7. SOURCEHI Fields.....................................................................................5-6
Table 5-8. DESTLO Register .....................................................................................5-7
Table 5-9. DESTLO Fields .........................................................................................5-7
Table 5-10. DESTHI Register.....................................................................................5-7
Table 5-11. DESTHI Fields ........................................................................................5-7
Table 5-12. MAX Register..........................................................................................5-8
Table 5-13. MAX Fields..............................................................................................5-8
Table 5-14. CTRL Register ........................................................................................5-9
Table 5-15. CTRL Fields ............................................................................................5-9
Table 5-16. DMA Data Width ...................................................................................5-10
Table 5-17. DMA Burst Size.....................................................................................5-10
Table 5-18. Constraints on CTRL Field Values Based on Stream Type..................5-11
Table 5-19. CURSHI Register..................................................................................5-12
Table 5-20. CURSHI Fields......................................................................................5-12
Table 5-21. CURSLO Register.................................................................................5-12