I
2
C Module LH79524/LH79525 User’s Guide
9-12 Version 1.0
1FULL
Full Flag Indicates that a byte of address or data has been received
on the I
2
C bus and written into the ICDATA register. This bit remains 1 until
automatically cleared when the ICDATA Register is read by software or until
the TXABORT bit is set to 1.
1 = A byte of address or data has been received on the I
2
C bus and written
into the ICDATA register
0 =
No address or data byte received
0INTR
Interrupt This bit indicates the source of the interrupt condition. This bit
remains 1 until reset by software. The source of the interrupt can be:
• A data byte has been received on the I
2
C bus and written to ICDATA
• A Stop condition has been detected
• The FULL flag is 1
• In Master mode, when the TXABORT flag is 1
• In Slave mode, when the RXABORT flag is 1
1 = Interrupt condition is active
0 = No interrupt
Table 9-17. ICSTAT Fields (Cont’d)
BITS NAME DESCRIPTION
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