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I/O Configuration LH79524/LH79525 User’s Guide

11-56 Version 1.0

Table of Contents

Default Chapter3
- Table of Contents3
Preface36
- Conventions and Terms36
- What's in this User's Guide41
Chapter 1 - Overview41
Chapter 2 - ADC and Brownout Detector41
Chapter 3 - Boot Controller41
Chapter 4 - Color LCD Controller41
Chapter 5 - DMA Controller41
Chapter 6 - Ethernet MAC41
Chapter 7 - External Memory Controller42
Chapter 8 - General Purpose Input/Output42
Chapter 11 - I/O Configuration42
Chapter 12 - Real Time Clock42
Chapter 13 - Reset, Clock Generation and Power Control42
Chapter 14 - Synchronous Serial Port42
Chapter 20 Appendix - Glossary43
Preface43
- Version43
Chapter 15 - Timers43
Chapter 16 - Uarts43
Chapter 17 - USB Device43
Chapter 18 - Vectored Interrupt Controller43
Chapter 19 - Watchdog Timer43
Chapter 1 - Overview44
- Table 1-1. LH79524/LH79525 Differences44
- Chapter 1 - Overview56
Chapter 2 - Analog-To-Digital Converter/Brownout Detector72
- Table 2-4. in + Mux Definition72
- Chapter 2 - Analog-To-Digital Converter/Brownout Detector76
Chapter 3 - Boot Controller88
- Theory of Operation88
- Chapter 4 - Color Liquid Crystal Display Controller97
  - Introduction97
    - Figure 4-2. Block Diagram of a Typical Advanced LCD Panel98
    - LCD Panel Architecture98
  - CLCDC Features99
Chapter 4 - Color Liquid Crystal Display Controller107
- Table 4-9. Color STN Intensities from Gray-Scale Modulation107
- Chapter 5 - Direct Memory Access Controller144
Chapter 5 - Direct Memory Access Controller149
- Table 5-4. SOURCELO Register149
- Table 5-5. SOURCELO Fields149
- Table 5-6. SOURCEHI Register149
- Table 5-7. SOURCEHI Fields149
- Register Definitions149
- Chapter 6 - Ethernet MAC Controller162
Chapter 6 - Ethernet MAC Controller200
- Table 6-40. MULTFRM Register200
Chapter 7 - External Memory Controller216
- Figure 7-1. External Memory Controller Block Diagram217
Chapter 8 - General Purpose Input/Output275
- Table 8-1. GPIO Ports275
- Theory of Operation275
- Table 8-2. LH79524 GPIO Multiplexing276
- Table 8-3. LH79525 GPIO Multiplexing279
- Table 8-4. GPIO Port Memory Map281
- Register Reference281
  - Register Descriptions282
Chapter 9 - I 2 C Module287
- Figure 9-2. I 2 C Bus Protocol288
Chapter 10 - I 2 S Converter303
- Transmission303
- Figure 10-7. I 2 S Slave Mode Transmission Block Diagram304
- Figure 10-8. I 2 S Slave Mode Transmission Timing Diagram305
- Reception305
  - Slave Mode Reception307
  - Suppression of SSPFSSIN308
- Interrupts309
  - Receive Interrupt310
  - Memory Map311
  - Table 10-2. CTRL Register312
  - Table 10-3. CTRL Register Definitions312
  - Register Descriptions312
  - Table 10-4. WSINV Functionality313
  - Table 10-5. STAT Register314
  - Table 10-6. STAT Register Definitions314
- Status Register (STAT)314
  - Interrupt Mask Set or Clear Register (IMSC)315
  - Table 10-7. IMSC Register315
  - Table 10-8. IMSC Register Definitions315
  - Raw Interrupt Status Register (RIS)316
  - Table 10-10. RIS Register Definitions316
  - Table 10-9. RIS Register316
  - Masked Interrupt Status Register (MIS)317
  - Table 10-11. MIS Register317
  - Table 10-12. MIS Register Definitions317
  - Interrupt Clear Register (ICR)318
  - Table 10-13. ICR Register318
  - Table 10-14. ICR Register Definitions318
- Resistor Configuration Control 1 Register (RESCTL1)323
- Table 11-6. MUXCTL3 Register324
- Table 11-7. MUXCTL3 Fields324
- Table 11-8. RESCTL3 Register324
- Table 11-9. RESCTL3 Fields324
- Multiplexing Control 3 Register (MUXCTL3)324
- Table 11-10. MUXCTL4 Register325
- Table 11-11. MUXCTL4 Fields325
- Multiplexing Control 4 Register (MUXCTL4)325
- Table 11-12. RESCTL4 Register326
- Table 11-13. RESCTL4 Fields326
- Resistor Configuration Control 4 Register (RESCTL4)326
- Table 11-14. MUXCTL5 Register327
- Table 11-15. MUXCTL5 Fields327
- Multiplexing Control 5 Register (MUXCTL5)327
- Table 11-16. RESCTL5 Register328
- Table 11-17. RESCTL5 Fields328
- Resistor Configuration Control 5 Register (RESCTL5)328
- Table 11-18. MUXCTL6 Register330
- Table 11-19. MUXCTL6 Fields330
- Multiplexing Control 6 Register (MUXCTL6)330
- Table 11-20. RESCTL6 Register331
- Table 11-21. RESCTL6 Fields331
- Resistor Configuration Control 6 Register (RESCTL6)331
- Table 11-22. MUXCTL7 Register332
- Table 11-23. MUXCTL7 Fields332
- Multiplexing Control 7 Register (MUXCTL7)332
- Table 11-24. RESCTL7 Register334
- Table 11-25. RESCTL7 Fields334
- Resistor Configuration Control 7 Register (RESCTL7)334
- Table 11-26. MUXCTL10 Register336
- Table 11-27. MUXCTL10 Fields336
- Multiplexing Control 10 Register (MUXCTL10)336
- Table 11-28. RESCTL10 Register338
- Table 11-29. RESCTL10 Fields338
- Resistor Configuration Control 10 Register (RESCTL10)338
- Table 11-30. MUXCTL11 Register340
- Table 11-31. MUXCTL11 Fields340
- Multiplexing Control 11 Register (MUXCTL11)340
- Table 11-32. RESCTL11 Register342
- Table 11-33. RESCTL11 Fields342
- Resistor Configuration Control 11 Register (RESCTL11)342
- Table 11-34. MUXCTL12 Register344
- Table 11-35. MUXCTL12 Fields344
- Multiplexing Control 12 Register (MUXCTL12)344
- Table 11-36. RESCTL12 Register345
- Table 11-37. RESCTL12 Fields345
- Resistor Configuration Control 12 Register (RESCTL12)345
- Table 11-38. RESCTL13 Register347
- Table 11-39. RESCTL13 Fields347
- Resistor Configuration Control 13 Register (RESCTL13)347
- Table 11-40. MUXCTL14 Register348
- Table 11-41. MUXCTL14 Fields348
- Multiplexing Control 14 Register (MUXCTL14)348
- Table 11-42. MUXCTL15 Register350
- Table 11-43. MUXCTL15 Fields350
- Table 11-44. RESCTL15 Register350
- Table 11-45. RESCTL15 Fields350
- Multiplexing Control 15 Register (MUXCTL15)350
- Table 11-46. RESCTL17 Register351
- Table 11-47. RESCTL17 Fields351
- Resistor Configuration Control 17 Register (RESCTL17)351
- Table 11-48. MUXCTL19 Register352
- Table 11-49. MUXCTL19 Fields352
- Multiplexing Control 19 Register (MUXCTL19)352
- Table 11-50. RESCTL19 Register354
- Table 11-51. RESCTL19 Fields354
- Resistor Configuration Control 19 Register (RESCTL19)354
  - Multiplexing Control 20 Register (MUXCTL20)356
  - Table 11-52. MUXCTL20 Register356
  - Table 11-53. MUXCTL20 Fields356
  - Resistor Configuration Control 20 Register (RESCTL20)358
  - Table 11-54. RESCTL20 Register358
  - Table 11-55. RESCTL20 Fields358
  - Multiplexing Control 21 Register (MUXCTL21)360
  - Table 11-56. MUXCTL21 Register360
  - Table 11-57. MUXCTL21 Fields360
  - Resistor Configuration Control 21 Register (RESCTL21)361
  - Table 11-58. RESCTL21 Register361
  - Table 11-59. RESCTL21 Fields361
  - Multiplexing Control 22 Register (MUXCTL22)362
  - Table 11-60. MUXCTL22 Register362
  - Table 11-61. MUXCTL22 Fields362
  - Resistor Configuration Control 22 Register (RESCTL22)364
  - Table 11-62. RESCTL22 Register364
  - Table 11-63. RESCTL22 Fields364
  - Multiplexing Control 23 Register (MUXCTL23)366
  - Table 11-64. MUXCTL23 Register366
  - Table 11-65. MUXCTL23 Fields366
  - Resistor Configuration Control 23 Register (RESCTL23)368
  - Table 11-66. RESCTL23 Register368
  - Table 11-67. RESCTL23 Fields368
  - Multiplexing Control 24 Register (MUXCTL24)370
  - Table 11-68. MUXCTL24 Register370
  - Table 11-69. MUXCTL24 Fields370
  - Resistor Configuration Control 24 Register (RESCTL24)371
  - Table 11-70. RESCTL24 Register371
  - Table 11-71. RESCTL24 Fields371
  - Multiplexing Control 25 Register (MUXCTL25)372
  - Table 11-72. MUXCTL25 Register372
  - Table 11-73. MUXCTL25 Fields373
  - Figure 12-1. RTC Block Diagram375
  - Theory of Operation375
    - Configuring the RTC for Use376
    - Table 12-1. RTC Register Summary377
    - Table 12-2. DR Register377
    - Table 12-3. DR Fields377
  - Register Reference377
    - Match Register (MR)378
    - Table 12-4. MR Register378
    - Table 12-5. MR Fields378
    - Table 12-6. LR Register378
    - Table 12-7. LR Fields378
    - Control Register (CR)379
    - Table 12-10. IMSC Register379
    - Table 12-11. IMSC Fields379
    - Table 12-8. CR Register379
    - Table 12-9. CR Fields379
    - Raw Interrupt Status Register (RIS)380
    - Table 12-12. RIS Register380
    - Table 12-13. RIS Fields380
    - Table 12-14. MIS Register380
    - Table 12-15. MIS Fields380
    - Interrupt Clear Register (ICR)381
    - Table 12-16. ICR Register381
    - Table 12-17. ICR Fields381
    - Figure 13-1. RCPC Block Diagram383
  - Theory of Operation383
    - System PLL and USB PLL Reset384
    - Figure 13-2. USB Clock Divider Chain385
    - Peripheral Block Clocks385
    - Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies386
    - Table 13-2. Clock and Enable States for Different Power Modes387
    - Stop2 Mode388
    - Table 13-3. RCPC Register Summary389
  - Register Reference389
    - Control Register (CTRL)390
    - Table 13-4. CTRL Register390
    - Table 13-5. CTRL Fields390
    - Identification Register (CHIPID)391
    - Table 13-6. CHIPID Register391
    - Table 13-7. CHIPID Fields391
    - Figure 13-3. Remap = 0B00392
    - Remap Control Register (REMAP)392
    - Table 13-8. REMAP Register392
    - Table 13-9. REMAP Fields392
    - Figure 13-4. Remap = 0B01393
    - Figure 13-5. Remap = 0B10393
    - Figure 13-6. Remap = 0B11394
    - Software Reset Register (SOFTRESET)395
    - Table 13-10. SOFTRESET Register395
    - Table 13-11. SOFTRESET Fields395
    - Reset Status Register (RSTSTATUS)396
    - Table 13-12. RSTSTATUS Register396
    - Table 13-13. RSTSTATUS Fields396
    - Reset Status Clear Register (RSTSTATUSCLR)397
    - Table 13-14. RSTSTATUSCLR Register397
    - Table 13-15. RSTSTATUSCLR Fields397
    - System Clock Prescaler Register (SYSCLKPRE)398
    - Table 13-16. SYSCLKPRE Register398
    - Table 13-17. SYSCLKPRE Fields398
    - Table 13-18. SYSCLKPRE Register Values398
    - CPU Clock Prescaler Register (CPUCLKPRE)399
    - Table 13-19. CPUCLKPRE Register399
    - Table 13-20. CPUCLKPRE Fields399
    - Table 13-21. CPUCLKPRE Register Values399
    - Peripheral Clock Control Register 0 (PCLKCTRL0)400
    - Table 13-22. PCLKCTRL0 Register400
    - Table 13-23. PCLKCTRL0 Fields400
    - Peripheral Clock Control Register 1 (PCLKCTRL1)401
    - Table 13-24. PCLKCTRL1 Register401
    - Table 13-25. PCLKCTRL1 Fields401
    - AHB Clock Control Register (AHBCLKCTRL)402
    - Table 13-26. AHBCLKCTRL Register402
    - Table 13-27. AHBCLKCTRL Fields402
    - Peripheral Clock Select Register 0 (PCLKSEL0)403
    - Table 13-28. PCLKSEL0 Register403
    - Table 13-29. PCLKSEL0 Fields403
    - Peripheral Clock Select Register 1 (PCLKSEL1)404
    - Table 13-30. PCLKSEL1 Register404
    - Table 13-31. PCLKSEL1 Fields404
    - Silicon Revision Register (SILICONREV)405
    - Table 13-32. SILICONREV Register405
    - Table 13-33. SILICONREV Fields405
    - LCD Clock Prescaler Register (LCDPRE)406
    - Table 13-34. LCDPRE Register406
    - Table 13-35. LCDPRE Fields406
    - Table 13-36. LCDPRE Register Values406
    - SSP Clock Prescaler Register (SSPPRE)407
    - Table 13-37. SSPPRE Register407
    - Table 13-38. SSPPRE Fields407
    - Table 13-39. SSPPRE Register Values407
    - ADC Clock Prescaler Register (ADCPRE)408
    - Table 13-40. ADCPRE Register408
    - Table 13-41. ADCPRE Fields408
    - Table 13-42. ADCPRE Register Values408
    - Table 13-43. USBPRE Register409
    - Table 13-44. USBPRE Fields409
    - Table 13-45. USBPRE Register Values409
    - USB Clock Prescaler Register (USBPRE)409
    - External Interrupt Configuration Register (INTCONFIG)410
    - Table 13-46. INTCONFIG Register410
    - Table 13-47. INTCONFIG Fields410
    - External Interrupt Clear Register (INTCLR)412
    - Table 13-48. INTCLR Register412
    - Table 13-49. INTCLR Fields412
    - Core Clock Configuration Register (CORECONFIG)413
    - Table 13-50. CORECONFIG Register413
    - Table 13-51. CORECONFIG Fields413
    - System PLL Control Register (SYSPLLCTL)414
    - Table 13-52. SYSPLLCTL Register414
    - Table 13-53. SYSPLLCTL Fields414
    - Table 13-54. USBPLLCTL Register415
    - Table 13-55. USBPLLCTL Fields415
    - USB PLL Control Register (USBPLLCTL)415
  - Theory of Operation416
    - Table 14-1. Feature Comparison417
    - Figure 14-1. SSP Timing Waveform Parameters418
    - Timing Waveforms418
    - Figure 14-2. Motorola SPI Frame Format (Continuous Transfer)419
    - Figure 14-4. Texas Instruments Synchronous Serial Frame Format (Single Transfer)420
    - Figure 14-5. Texas Instruments Synchronous Serial Frame Format (Continuous Transfers)420
    - Figure 14-6. Microwire Frame Format (Single Transfer)421
    - National Semiconductor Frame Format421
    - Clock Generation422
    - Figure 14-7. Microwire Frame Format (Continuous Transfers)422
Chapter 14 - Synchronous Serial Port423
- Transmit Interrupt423
- Table 14-2. SSP Register Summary424
- Memory Map424
- Table 14-3. CTRL0 Register425
- Table 14-4. CTRL0 Fields425
- Register Descriptions425
- Table 14-5. CTRL1 Register427
- Table 14-6. CTRL1 Fields427
- Control Register 1 (CTRL1)427
- Table 14-7. DR Register428
- Table 14-8. DR Fields428
- Data Register – Receive/Transmit FIFO Register (DR)428
- Table 14-9. SR Register429
- Table 14-10. SR Fields429
- Status Register (SR)429
- Table 14-11. CPSR Register430
- Table 14-12. CPSR Fields430
- Clock Prescale Register (CPSR)430
- Table 14-13. IMSC Register431
- Table 14-14. IMSC Fields431
- Interrupt Mask Set and Clear Register (IMSC)431
- Table 14-15. RIS Register432
- Table 14-16. RIS Fields432
- Raw Interrupt Status Register (RIS)432
- Table 14-17. MIS Register433
- Table 14-18. MIS Fields433
- Masked Interrupt Status Register (MIS)433
- Table 14-19. ICR Register434
- Table 14-20. ICR Fields434
- Interrupt Clear Register (ICR)434
- Table 14-21. DCR Register435
- Table 14-22. DCR Fields435
- DMA Control Register (DCR)435
- Figure 15-1. Timer Block Diagram437
- Theory of Operation437
  - Counter Clear Upon Compare Match438
  - Figure 15-2. Count Clock Timing (HCLK in Phase with CTCLK)438
  - Figure 15-3. Count Clock Timing (HCLK Not in Phase with CTCLK)438
  - Capture Signal Sampling439
    - Figure 15-5. PWM Output Signal Timing440
    - Timer Interrupts440
    - Register Reference441
    - Table 15-1. Timer 0 Register Summary441
    - Table 15-2. Timer 1 Register Summary441
    - Table 15-3. Timer 2 Register Summary441
    - Register Descriptions442
    - Table 15-4. CTRL0 Register442
    - Table 15-5. CTRL0 Register Definitions442
    - Table 15-6. CMP_CAP_CTRL0 Register443
    - Table 15-7. CMP_CAP_CTRL0 Register Definitions443
    - Timer 0 Compare/Capture Control Register (CMP_CAP_CTRL0)443
    - Table 15-8. INTEN0 Register445
    - Table 15-9. INTEN0 Register Definitions445
    - Timer 0 Interrupt Control Register (INTEN0)445
    - Table 15-10. STATUS0 Register446
    - Table 15-11. STATUS0 Register Definitions446
    - Timer 0 Status Register (STATUS0)446
    - Table 15-12. CNT0 Register447
    - Table 15-13. CNT0 Register Definitions447
    - Timer 0 Counter Register (CNT0)447
    - Table 15-14. T0Cmpn Registers448
    - Table 15-15. T0Cmpn Register Definitions448
    - Timer 0 Compare Registers (T0Cmpn)448
    - Table 15-16. Capn Register449
    - Table 15-17. Capn Register Definitions449
    - Timer 0 Capture Registers (Capn)449
    - Table 15-18. CTRL1 Register450
    - Table 15-19. CTRL1 Register Definitions450
    - Timer 1 Control Register (CTRL1)450
    - Table 15-20. INTEN1 Register452
    - Table 15-21. INTEN1 Register Definitions452
    - Timer 1 Interrupt Control Register (INTEN1)452
    - Table 15-22. STATUS1 Register453
    - Table 15-23. STATUS1 Register Definitions453
    - Timer 1 Status Register (STATUS1)453
    - Table 15-24. CNT1 Register454
    - Table 15-25. CNT1 Register Definitions454
    - Timer 1 Counter Register (CNT1)454
    - Table 15-26. T1Cmpn Registers455
    - Table 15-27. T1Cmpn Register Definitions455
    - Timer 1 Compare Registers (T1Cmpn)455
    - Table 15-28. T1Capn Register456
    - Table 15-29. T1Capn Register Definitions456
    - Timer 1 Capture Registers (T1Capn)456
    - Table 15-30. CTRL2 Register457
    - Table 15-31. CTRL2 Register Definitions457
    - Timer 2 Control Register (CTRL2)457
    - Table 15-32. INTEN2 Register459
    - Table 15-33. INTEN2 Register Definitions459
    - Timer 2 Interrupt Control Register (INTEN2)459
    - Table 15-34. STATUS2 Register460
    - Table 15-35. STATUS2 Register Definitions460
    - Timer 2 Status Register (STATUS2)460
    - Table 15-36. CNT2 Register461
    - Table 15-37. CNT2 Register Definitions461
    - Timer 2 Counter Register (CNT2)461
    - Table 15-38. T2Cmpn Registers462
    - Table 15-39. T2Cmpn Register Definitions462
    - Timer 2 Compare Registers (T2Cmpn)462
    - Table 15-40. T2Capn Register463
    - Table 15-41. T2Capn Register Definitions463
    - Timer 2 Capture Registers (T2Capn)463
    - Figure 16-1. UART0, UART1, and UART2 Block Diagram465
    - Theory of Operation465
  - Figure 15-4. Capture Signal Synchronization Timing439
  - Transmitting Data466
  - Nine-Bit Mode467
  - On-Chip DMA Capabilities468
  - Table 16-1. Control Bits to Enable and Disable Hardware Flow Control469
  - Interrupts470
  - Table 16-2. UART Register Summary470
  - Register Definitions471
    - Table 16-3. UARTDR Register471
    - Table 16-4. UARTDR Fields471
    - Receive Status/Error Clear Register (UARTRSR/UARTECR)472
    - Table 16-5. Nine-Bit Mode/Parity Bit Table472
    - Table 16-6. UARTRSR/UARTECR Register (Write Operations)472
    - Table 16-7. UARTRSR/UARTECR Fields (Write Operations)472
    - Table 16-8. UARTRSR/UARTECR Register (Read Operations)473
    - Table 16-9. UARTRSR/UARTECR Fields (Read Operations)473
    - Flag Register (UARTFR)474
    - Table 16-10. UARTFR Register474
    - Table 16-11. UARTFR Fields474
    - Irda Low-Power Counter Register (UARTILPR)475
    - Table 16-12. UARTILPR Register475
    - Table 16-13. UARTILPR Fields475
    - Integer Baud Rate Divisor Register (UARTIBRD)476
    - Table 16-14. UARTIBRD Register476
    - Table 16-15. UARTIBRD Fields476
    - Fractional Baud Rate Divisor Register (UARTFBRD)477
    - Table 16-16. UARTFBRD Register477
    - Table 16-17. UARTFBRD Fields477
    - Table 16-18. Bit Rates and Their Corresponding Divisors477
    - Line Control Register (UARTLCR_H)478
    - Table 16-20. UARTLCR_H Fields479
    - Table 16-21. Truth Table for 9BIT, SPS, EPS, and PEN Bits479
    - Table 16-22. UARTCR Register480
    - Table 16-23. UARTCR Fields480
    - UART Control Register (UARTCR)480
    - Interrupt FIFO Level Select Register (UARTIFLS)482
    - Table 16-24. UARTIFLS Register482
    - Table 16-25. UARTIFLS Fields482
    - Interrupt Mask Set/Clear Register (UARTIMSC)483
    - Table 16-26. UARTIMSC Register483
    - Table 16-27. UARTIMSC Fields483
    - Raw Interrupt Status Register (UARTRIS)485
    - Table 16-28. UARTRIS Register485
    - Table 16-29. UARTRIS Fields485
    - Masked Interrupt Status Register (UARTMIS)487
    - Table 16-30. UARTMIS Register487
    - Table 16-31. UARTMIS Fields487
    - Interrupt Clear Register (UARTICR)489
    - Table 16-32. UARTICR Register489
    - Table 16-33. UARTICR Fields489
    - Table 16-34. DMACTRL Register490
    - Table 16-35. DMACTRL Fields490
    - UART0 DMA Control Register (DMACTRL)490
    - Figure 17-1. USB Block Diagram491
    - Theory of Operation491
    - Figure 17-2. USB Communication Endpoints492
    - Table 17-1. Endpoint Function492
    - Isochronous Endpoints493
    - Table 17-2. Endpoint FIFO Characteristics493
  - DMA Interface494
  - DMA Operation495
    - DMA Mode 1: out Endpoints496
    - DMA Mode 1: in Endpoints497
    - Memory Map498
    - Table 17-3. USB Register Summary498
    - Register Definitions500
    - Table 17-4. FAR Register500
    - Table 17-5. FAR Fields500
    - Power Management Register (PMR)501
    - Table 17-6. PMR Register501
    - Table 17-7. PMR Fields501
    - Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR)502
    - Table 17-8. IIR Register502
    - Table 17-9. IIR Fields502
    - Interrupt Register for out Endpoint 1 and 2 (OIR)503
    - Table 17-10. OIR Register503
    - Table 17-11. OIR Fields503
    - Interrupt Register for Common USB Interrupts (UIR)504
    - Table 17-12. UIR Register504
    - Table 17-13. UIR Fields504
    - IN Interrupt Enable Register (IIE)505
    - Table 17-14. IIE Register505
    - Table 17-15. IIE Fields505
    - OUT Interrupt Enable Register (OIE)506
    - Table 17-16. OIE Register506
    - Table 17-17. OIE Fields506
    - Interrupt Enable Register (UIE)507
    - Table 17-18. UIE Register507
    - Table 17-19. UIE Fields507
    - Frame Number Registers (Framex)508
    - Table 17-20. FRAME1 Register508
    - Table 17-21. FRAME2 Register508
    - Table 17-22. FRAME1 Fields508
    - Table 17-23. FRAME2 Fields508
    - Table 17-24. INDEX Register509
    - Table 17-25. INDEX Fields509
  - Indexed Registers509
    - IN Maximum Packet Size Register (INMAXP)510
    - Table 17-26. INMAXP Register510
    - Table 17-27. INMAXP Fields510
    - Control Status Register for EP 0 (CSR0)511
    - Table 17-28. CSR0 Register511
    - Table 17-29. CSR0 Fields511
    - Control Status Register 1 for in EP 1, 2, and 3 (INCSR1)513
    - Table 17-30. INCSR1 Register513
    - Table 17-31. INCSR1 Fields513
    - Control Status Register 2 for in EP 1, 2, and 3 (INCSR2)515
    - Table 17-32. INCSR2 Register515
    - Table 17-33. INCSR2 Fields515
    - OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP)516
    - Table 17-34. OUTMAXP Register516
    - Table 17-35. OUTMAXP Fields516
    - Control Status Register 1 for out EP1 and EP2 (OUTSCSR1)517
    - Table 17-36. OUTCSR1 Register517
    - Table 17-37. OUTCSR1 Fields517
    - Control Status Register 2 for out EP1 and EP 2 (OUTCSR2)519
    - Table 17-38. OUTCSR2 Register519
    - Table 17-39. OUTCSR2 Fields519
    - Table 17-40. OUTCOUNT0 Register520
    - Table 17-41. OUTCOUNT0 Fields520
    - Table 17-42. OUTCOUNT1 Register520
    - Table 17-43. OUTCOUNT1 Fields520
    - Table 17-44. OUTCOUNT2 Register521
    - Table 17-45. OUTCOUNT2 Fields521
    - Table 17-46. FIFO Register521
    - Table 17-47. COUNT1 Fields521
    - Pending DMA Interrupts Register (INTR)522
    - Table 17-48. INTR Register522
    - Table 17-49. INTR Fields522
    - DMA Channel X Control Register (Cntlx)523
    - Table 17-50. Cntlx Register523
    - Table 17-51. Cntlx Fields523
    - DMA Channel X AHB Memory Address Register524
    - Table 17-52. Addrx Register524
    - Table 17-53. Addrx Fields524
    - Table 17-54. Countx Register524
    - Table 17-55. Countx Fields524
    - Theory of Operation525
    - Table 18-1. Interrupt Assignments526
  - VIC Interrupt Listing526
  - Vectored Interrupts527
  - Clearing Interrupts528
  - Register Reference529
  - Table 18-2. VIC Register Summary529
  - Register Descriptions530
    - Table 18-3. IRQSTATUS Register530
    - Table 18-4. IRQSTATUS Fields530
    - Table 18-5. FIQSTATUS Register531
    - Table 18-6. FIQSTATUS Fields531
    - Table 18-7. RAWINTR Register531
    - Table 18-8. RAWINTR Fields531
    - Interrupt Select Register (INTSELECT)532
    - Table 18-10. INTSELECT Fields532
    - Table 18-11. INTENABLE Register532
    - Table 18-12. INTENABLE Fields532
    - Interrupt Enable Clear Register (INTENCLEAR)533
    - Table 18-13. INTENCLEAR Register533
    - Table 18-14. INTENCLEAR Fields533
    - Software Interrupt Register (SOFTINT)534
    - Table 18-15. SOFTINT Register534
    - Table 18-16. SOFTINT Fields534
    - Software Interrupt Clear Register (SOFTINTCLEAR)535
    - Table 18-17. SOFTINTCLEAR Register535
    - Table 18-18. SOFTINTCLEAR Fields535
    - Table 18-19. VECTADDR Register536
    - Table 18-20. VECTADDR Fields536
    - Table 18-21. DEFVECTADDR Register536
    - Table 18-22. DEFVECTADDR Fields536
    - Vector Address Register (VECTADDR)536
    - Table 18-23. Vectaddrx Registers537
    - Table 18-24. Vectaddrx Fields537
    - Vector Address Registers (Vectaddrx)537
    - Table 18-25. Vectctrlx Registers538
    - Table 18-26. Vectctrlx Fields538
    - Vector Control Registers (Vectctrlx)538
    - Interrupt Test Output Register (ITOP)539
    - Table 18-27. ITOP Register539
    - Table 18-28. ITOP Fields539
    - Theory of Operation540
    - Figure 19-1. Watchdog Timer Block Diagram541
  - Table 18-9. INTSELECT Register532
Chapter 19 - Watchdog Timer541
- WDT Operation Details542
- Table 19-1. Watchdog Timer Memory Map543
- Register Reference543
- Table 19-2. CTL Register544
- Table 19-3. CTL Fields544
- Register Descriptions544
Chapter 18 - Vectored Interrupt Controller541

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