LH79524/LH79525 User’s Guide Timers
Version 1.0 15-23
10:9 CMP0
Output Value Select Timer/Counter Operation: Programs the value (when a
compare match occurs) output on CTCMP2A when the CNT2 Register matches
the T2CMP0 Register.
00 = No change occurs to the output CTCMP2A
01 = Output 0 to CTCMP2A
10 = Output 1 to CTCMP2A
11 = Toggle the output to CTCMP2A
PWM Operation:
00 = Invalid
01 = Active LOW PWM output polarity
10 = Active HIGH PWM output polarity
11 = Invalid
IMPORTANT: CMP1 and CMP0 must be programmed to the same polarity.
8:7 CAPB
Input Edge Select Selects the rising edge, falling edge, both edges, or ignores
all changes of the input signal that is used as the capture trigger. This field and
the capture function are inactive in PWM mode.
00 = Capture input CTCAP2B is ignored
01 = Rising edge of CTCAP2B
10 = Falling edge of CTCAP2B
11 = Both edges of CTCAP2B
6:5 CAPA
Input Edge Select Selects the rising edge, falling edge, both edges, or ignores
all changes of the input signal that is used as the capture trigger. This field and
the capture function are inactive in PWM mode.
00 = Capture input CTCAP2A is ignored
01 = Rising edge of CTCAP2A
10 = Falling edge of CTCAP2A
11 = Both edges of CTCAP2A
4:2 SEL
Count Clock Select Specifies the timer clock divisor. The timer must be
stopped (with the CS bit) before programming the divisor.
000 = HCLK/2
001 = HCLK/4
010 = HCLK/8
011 = HCLK/16
100 = HCLK/32
101 = HCLK/64
110 = HCLK/128
111 = CTCLK
1CS
Start/Stop Timer 2 Specifies whether Timer 2 count is stopped or started. This
bit must be programmed to 0 before programming the SEL field in this register.
For more information, see Section 15.1.1.
0 = Stop Timer 2
1 = Start Timer 2
0 CCL
Timer 2 Count Clear Programming a 1 clears the timer count value. This bit
always reads as 0.
1 = Clears CNT2 contents to 0x0000
0 = Ignored; no effect
Table 15-31. CTRL2 Register Definitions (Cont’d)
BITS NAME DESCRIPTION
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